H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2006
11/23/2006	US20060264595 Coating a silicon wafer with the liquid coating of polysiloxane copolymer coating film; heat curing the coating film
11/23/2006	US20060264343 Cleaning method and solution for cleaning a wafer in a single wafer process
11/23/2006	US20060264158 Apparatus for polishing wafer and process for polishing wafer
11/23/2006	US20060264157 Wafer polishing apparatus and method for polishing wafers
11/23/2006	US20060264069 Method of forming quantum-mechanical memory and computational devices
11/23/2006	US20060264068 Method for fabricating semiconductor device and semiconductor substrate
11/23/2006	US20060264067 Surface pre-treatment for enhancement of nucleation of high dielectric constant materials
11/23/2006	US20060264066 Multilayer multicomponent high-k films and methods for depositing the same
11/23/2006	US20060264065 Sacrificial styrene benzocyclobutene copolymers for making air gap semiconductor devices
11/23/2006	US20060264064 Zirconium-doped tantalum oxide films
11/23/2006	US20060264063 Deposition of tensile and compressive stressed materials for semiconductors
11/23/2006	US20060264062 Method using TEOS ramp-up during TEOS/ozone CVD for improved gap-fill
11/23/2006	US20060264061 Solid source precursor delivery system
11/23/2006	US20060264060 Low temperature plasma deposition process for carbon layer deposition
11/23/2006	US20060264059 Semiconductor device, method for manufacturing semiconductor device and gas for plasma cvd
11/23/2006	US20060264058 Liquid-based gravity-driven etching-stop technique for controlling structure dimension
11/23/2006	US20060264057 Method and apparatus for fabricating a memory device with a dielectric etch stop layer
11/23/2006	US20060264056 Method and apparatus for fabricating a memory device with a dielectric etch stop layer
11/23/2006	US20060264055 Methods for controlling feature dimensions in crystalline substrates
11/23/2006	US20060264054 Method for etching a trench in a semiconductor substrate
11/23/2006	US20060264053 Method of aligning nanotubes and wires with an etched feature
11/23/2006	US20060264052 Method of forming a platinum pattern
11/23/2006	US20060264051 Method for formng impurity-introduced layer, method for cleaning object to be processed apparatus for introducing impurity and method for producing device
11/23/2006	US20060264050 Method and apparatus for chemical mixing in a single wafer process
11/23/2006	US20060264049 Spin-printing of etchants and modifiers
11/23/2006	US20060264048 Interconnect Structure Diffusion Barrier With High Nitrogen Content
11/23/2006	US20060264047 Formation of self-aligned contact plugs
11/23/2006	US20060264046 Method of manufacturing semiconductor device and semiconductor device
11/23/2006	US20060264045 Method and apparatus for preventing ALD reactants from damaging vacuum pumps
11/23/2006	US20060264044 Chemical vapor deposited film based on a plasma cvd method and method of forming the film
11/23/2006	US20060264043 Electroless deposition process on a silicon contact
11/23/2006	US20060264042 Interconnect structure including a silicon oxycarbonitride layer
11/23/2006	US20060264041 Microelectronic devices, methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
11/23/2006	US20060264040 Semiconductor device
11/23/2006	US20060264039 Selective deposition of fine particles
11/23/2006	US20060264038 Method for forming barrier film and method for forming electrode film
11/23/2006	US20060264037 Barrier layer, IC via, and IC line forming methods
11/23/2006	US20060264036 Line level air gaps
11/23/2006	US20060264035 Crack stop trenches in multi-layered low-k semiconductor devices
11/23/2006	US20060264034 Semiconductor device
11/23/2006	US20060264033 Dual damascene patterning method
11/23/2006	US20060264032 Formation of self-aligned contact plugs
11/23/2006	US20060264031 Method for depositing tungsten-containing layers by vapor deposition techniques
11/23/2006	US20060264030 Wire structure and forming method of the same
11/23/2006	US20060264029 Low inductance via structures
11/23/2006	US20060264028 Energy beam treatment to improve the hermeticity of a hermetic layer
11/23/2006	US20060264027 Air gap interconnect structure and method thereof
11/23/2006	US20060264026 Dendrite growth control circuit
11/23/2006	US20060264025 Stacked semiconductor device and method of manufacturing the same
11/23/2006	US20060264024 Integrated circuit with substantially perpendicular wire bonds
11/23/2006	US20060264023 Die-wafer package and method of fabricating same
11/23/2006	US20060264022 Semiconductor device
11/23/2006	US20060264021 Offset solder bump method and apparatus
11/23/2006	US20060264020 Formation of a masking layer on a dielectric region to facilitate formation of a capping layer on electrically conductive regions separated by the dielectric region
11/23/2006	US20060264019 Method of forming integrated circuitry
11/23/2006	US20060264018 Masking methods
11/23/2006	US20060264017 Method of manufacturing semiconductor device
11/23/2006	US20060264016 Active mask lithography
11/23/2006	US20060264015 Emits patterned energy flux in response to energy input; photomasks
11/23/2006	US20060264014 Structures, materials and methods for fabrication of nanostructures
11/23/2006	US20060264013 Method for implanting ions to a wafer for manufacturing of semiconductor device and method of fabricating graded junction using the same
11/23/2006	US20060264012 Plasma processing, deposition, and ALD methods
11/23/2006	US20060264011 Nitride-based compound semiconductor, method of cleaning a compound semiconductor, method of producing the same, and substrate
11/23/2006	US20060264010 Methods of forming layers comprising epitaxial silicon
11/23/2006	US20060264009 Method for significant reduction of dislocations for a very high A1 composition A1GaN layer
11/23/2006	US20060264008 Surface treatment after selective etching
11/23/2006	US20060264007 High quality oxide on an epitaxial layer
11/23/2006	US20060264006 Method and apparatus for RFID device assembly
11/23/2006	US20060264005 Silicon substrate processing method for observing defects in semiconductor devices and defect-detecting method
11/23/2006	US20060264004 Method of detachable direct bonding at low temperatures
11/23/2006	US20060264003 Trench isolation structure in a semiconductor device and method for fabricating the same
11/23/2006	US20060264002 Methods for increasing photo-alignment margins
11/23/2006	US20060264001 Structures with increased photo-alignment margins
11/23/2006	US20060264000 Methods for increasing photo-alignment margins
11/23/2006	US20060263999 Semiconductor capacitor structure and method to form same
11/23/2006	US20060263998 Semiconductor capacitor structure and method to form same
11/23/2006	US20060263997 Semiconductor capacitor structure and method to form same
11/23/2006	US20060263996 Semiconductor capacitor structure and method to form same
11/23/2006	US20060263995 Semiconductor capacitor structure and method to form same
11/23/2006	US20060263994 Semiconductors bonded on glass substrates
11/23/2006	US20060263993 Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation
11/23/2006	US20060263992 Method of forming the N-MOS and P-MOS gates of a CMOS semiconductor device
11/23/2006	US20060263991 Semiconductor device having shallow trench isolation structure and method of manufacturing the same
11/23/2006	US20060263990 Methods to form oxide-filled trenches
11/23/2006	US20060263989 Semiconductor device and fabrication method therefor
11/23/2006	US20060263988 Semiconductor device
11/23/2006	US20060263987 Methods of forming fusible devices
11/23/2006	US20060263986 Semiconductor device
11/23/2006	US20060263985 Method of fabricating a semiconductor device
11/23/2006	US20060263984 Vertical nanotransistor, method for producing the same and memory assembly
11/23/2006	US20060263983 Vertical transistor with horizontal gate layers
11/23/2006	US20060263982 Method of fabricating semiconductor device
11/23/2006	US20060263981 DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
11/23/2006	US20060263980 Method for making a semiconductor device including a floating gate memory cell with a superlattice channel
11/23/2006	US20060263979 Methods of forming devices associated with semiconductor constructions
11/23/2006	US20060263978 Fabricating method of a flash memory cell
11/23/2006	US20060263977 Methods of forming integrated circuit electrodes and capacitors by wrinkling a layer that includes a high percentage of impurities
11/23/2006	US20060263976 Semiconductor device with capacitor structure for improving area utilization
11/23/2006	US20060263975 Method for making a trench memory cell
11/23/2006	US20060263974 Methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cell

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