Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2007
09/06/2007US20070207572 CMOS Device Having Different Amounts of Nitrogen in the NMOS Gate Dielectric Layers and PMOS Gate Dielectric Layers
09/06/2007US20070207571 Method for manufacturing semiconductor device
09/06/2007US20070207570 Apparatuses and methods for forming identifying characters on semiconductor device and wafers
09/06/2007US20070207569 Biocompatible bonding method and electronics package suitable for implantation
09/06/2007US20070207568 SiP module with a single sided lid
09/06/2007US20070207567 Method of Base Formation in a Bicmos Process
09/06/2007US20070207566 Method of fabricating backside illuminated image sensor
09/06/2007US20070207565 Processes for forming photovoltaic features
09/06/2007US20070207564 Method for manufacturing a semiconductor device
09/06/2007US20070207563 Method for fabricating optical sensitive layer of solar cell having silicon quantum dots
09/06/2007US20070207562 Method of Forming a Micromachined Device Using an Assisted Release
09/06/2007US20070207561 InN/TiO2 photosensitized electrode
09/06/2007US20070207560 Components and methods for use in electro-optic displays
09/06/2007US20070207559 Fabrication method of semiconductor integrated circuit device
09/06/2007US20070207558 Integrated circuit memory system with dummy active region
09/06/2007US20070207557 Semiconductor chip mounting substrate, a method of producing the same, and a method of mounting a semiconductor chip
09/06/2007US20070207556 Manufacturing method of non-volatile memory
09/06/2007US20070207487 Photoelectrochemical synthesis of high density combinatorial polymer arrays
09/06/2007US20070207393 Photomask formation method, photomask, and semiconductor device fabrication method
09/06/2007US20070207322 Semiconductor encapsulating epoxy resin composition and semiconductor device
09/06/2007US20070207267 Disposable liners for etch chambers and etch chamber components
09/06/2007US20070207014 Substrate processing apparatus
09/06/2007US20070206656 On chip temperature measuring and monitoring circuit and method
09/06/2007US20070206416 Nonvolatile semiconductor memory device
09/06/2007US20070206415 Non-volatile memory cell and non-volatile memory device using said cell
09/06/2007US20070206366 Method for embedding a component in a base
09/06/2007US20070206264 Image Forming Method and Apparatus
09/06/2007US20070206173 Reticle protection member, reticle carrying device, exposure device and method for carrying reticle
09/06/2007US20070206172 Lithographic apparatus and device manufacturing method
09/06/2007US20070206167 Exposure Method and Apparatus, and Device Manufacturing Method
09/06/2007US20070205783 Sheet-Like Probe, Method Of Producing The Probe, And Application Of The Probe
09/06/2007US20070205727 Plasma-generation power-supply device
09/06/2007US20070205707 Electronic device containing a carbon nanotube
09/06/2007US20070205517 Semiconductor Devices and Method for Fabricating the Same
09/06/2007US20070205512 Solder bump structure for flip chip package and method for manufacturing the same
09/06/2007US20070205501 Package warpage control
09/06/2007US20070205494 Chip-size package structure and method of the same
09/06/2007US20070205490 Method for Production of Semiconductor Chip, and Semiconductor Chip
09/06/2007US20070205486 Thin film capacitor device used for a decoupling capacitor and having a resistor inside
09/06/2007US20070205481 Manufacturing method for semiconductor device, semiconductor device and semiconductor wafer
09/06/2007US20070205480 Semiconductor Device
09/06/2007US20070205479 Method for attaching a flexible structure to a device and a device having a flexible structure
09/06/2007US20070205476 Printed magnetic rom-mprom
09/06/2007US20070205472 Formation of a disposable spacer to post dope a gate conductor
09/06/2007US20070205468 Complementary Metal Oxide Semiconductor Transistor Technology Using Selective Epitaxy of a Strained Silicon Germanium Layer
09/06/2007US20070205465 Semiconductor device and fabrication method thereof
09/06/2007US20070205460 Hybrid orientation scheme for standard orthogonal circuits
09/06/2007US20070205457 Semiconductor memory device with bit line of small resistance and manufacturing method thereof
09/06/2007US20070205452 Method for forming a metal oxide film
09/06/2007US20070205437 Method for the production of a semiconductor substrate comprising a plurality of gate stacks on a semiconductor substrate, and corresponding semiconductor structure
09/06/2007US20070205435 Versatile system for optimizing current gain in bipolar transistor structures
09/06/2007US20070205434 Methodology for recovery of hot carrier induced degradation in bipolar devices
09/06/2007US20070205433 Insulating gate AlGaN/GaN HEMTs
09/06/2007US20070205424 Nitride semiconductor light emitting device, method of manufacturing nitride semiconductor light emitting device, and nitride semiconductor transistor device
09/06/2007US20070205421 Semiconductor optical devices and method for forming
09/06/2007US20070205419 Semiconductor device and its manufacturing method
09/06/2007US20070205415 Semiconductor device and manufacturing method thereof
09/06/2007US20070205414 Method for forming an improved low power SRAM contact
09/06/2007US20070205413 Semiconductor device and manufacturing method thereof
09/06/2007US20070205249 Compliant Wirebond Pedestal
09/06/2007US20070204959 Substrate processing method and material for electronic device
09/06/2007US20070204957 Plasma processing of large workpieces
09/06/2007US20070204956 Method of manufacturing a semiconductor device and wet processing apparatus
09/06/2007US20070204905 InN/InP/TiO2 photosensitized electrode
09/06/2007US20070204885 Substrate processing apparatus for resist film removal
09/06/2007US20070204795 System and methods for manufacturing a liquid crystal device
09/06/2007US20070204794 Method and apparatus for an improved baffle plate in a plasma processing system
09/06/2007US20070204792 Vaporizer with Integral Diaphragm
09/06/2007US20070204790 Solvents and new method for the synthesis of cdse semiconductor nanocrystals
09/06/2007US20070204789 Method For Evaluating Crystal Defects Of Silicon Wafer
09/06/2007US20070204724 Aerosol method and apparatus, particulate products, and electronic devices made therefrom
09/06/2007US20070204447 Intralevel decoupling capacitor, method of manufacture and testing circuit of the same
09/06/2007DE19723202B4 Herstellungsverfahren eines rißfesten Halbleiterbauteils und Herstellungsgerät hierfür Process for manufacturing a rupture resistant semiconductor device and manufacturing apparatus therefor
09/06/2007DE19648729B4 Matrix-Anordnung einer Flüssigkristallanzeige mit aktiver Matrix und Herstellverfahren dafür Matrix arrangement of a liquid crystal active matrix display and manufacturing methods for
09/06/2007DE19516446B4 Verfahren zur Herstellung eines Dünnschichthalbleiterbauelements über einer TCO-Elektrodenschicht A method for producing a thin film semiconductor device on a TCO electrode layer
09/06/2007DE112005002579T5 Polierzusammensetzung für Siliciumscheibe Polishing composition for silicon wafer
09/06/2007DE112005002474T5 Verfahren und System zum dynamischen Einstellen der Messdatennahme auf der Grundlage der verfügbaren Messkapazität Method and system for dynamically adjusting the measurement data acquisition based on the available measured capacitance
09/06/2007DE112005002441T5 Verfahren zum Zerteilen von Halbleiter-Wafern und Verfahren zum Herstellen von Halbleiterbauelementen A method for cutting semiconductor wafers and methods of manufacturing of semiconductor devices
09/06/2007DE112005002353T5 Verfahren zur Herstellung von Sammelleitungen aus Kupfer Process for the preparation of collecting lines of copper
09/06/2007DE112005002313T5 Verfahren zur Optimierung der Implantierungsbedingungen zum Minimieren der dadurch gebildeten Kanalisierungen und Strukturen Method for optimizing the Implantierungsbedingungen for minimizing the canalizations and structures formed thereby
09/06/2007DE112005000704T5 Nicht-planarer Bulk-Transistor mit verspanntem Kanal mit erhöhter Mobilität und Verfahren zur Herstellung Non-planar bulk transistor having strained channel with increased mobility and process for preparing
09/06/2007DE112004000872T5 Anordnung und Verfahren zum Ausbilden eines Trench-MOSFETs mit Selbstausrichtungsmerkmalen Arrangement and method for forming a trench MOSFET having self-aligning features
09/06/2007DE10353326B4 Substratverarbeitungsgerät und Verfahren zum Verarbeiten eines Substrats unter Steuerung der Kontaminierung in einem Substrattransfermodul A substrate processing apparatus and method for processing a substrate under the control of contamination in a substrate transfer module
09/06/2007DE10351017B4 Phasenwechsel-Speicherzellen und Verfahren zur Herstellung derselben Phase change memory cells and methods of manufacturing the same
09/06/2007DE10337509B4 Gerät zur Herstellung von Halbleitern Apparatus for production of semiconductors
09/06/2007DE10308860B4 Verfahren zum Vereinzeln von Halbleiterscheiben mit frei liegenden mikromechanischen Strukturen zu Chips A method for singulating semiconductor wafers with exposed micromechanical structures into chips
09/06/2007DE10260755B4 Verfahren zur Bildung eines Strukturelementes auf einem Wafer mittels einer Maske und einer ihr zugeordneten Trim-Maske A method for forming a structural element on a wafer with a mask and a trim mask assigned
09/06/2007DE102007010001A1 Chip und Verfahren zum Trennen von Wafern in Chips Chip and method of separating wafers into chips
09/06/2007DE102007008223A1 System und Verfahren zum Entfernen von Fremdpartikeln von einer Halbleitervorrichtung System and method for removing foreign particles from a semiconductor device
09/06/2007DE102007007071A1 Halbleiteranordnungen und Verfahren zur Herstellung derselben Semiconductor devices and methods of manufacturing the same
09/06/2007DE102007005920A1 Leiterplatte mit einem eingebetteten Nacktchip und Verfahren derselben Circuit board with an embedded bare chip and method thereof
09/06/2007DE102007005332A1 Semiconductor component e.g. metal oxide semiconductor field-effect transistor, manufacturing method, involves implementing annealing process in impurity implanted area in order to form impurity doped area
09/06/2007DE102007005328A1 Complementary metal oxide semiconductor device e.g. complementary metal oxide semiconductor transistor, has gate stacks whose second conductive layers are formed of different conductive materials
09/06/2007DE102006013812A1 Dünnfilmkondensator und Verfahren zur Herstellung desselben, elektronische Anordnung und Leiterplatte Thin film capacitor and methods of manufacturing the same, electronic device and printed circuit board
09/06/2007DE102006010981A1 Halbleiterbauelement und Herstellungsverfahren A semiconductor device and manufacturing method
09/06/2007DE102006010463A1 Chip stack arrangement for use in semiconductor field, has two chips with upper and lower sides, and electrically non-conductive supporting units arranged between lower side of one chip and upper side of substrate and made of epoxy resin
09/06/2007DE102006009723A1 Verfahren zum Herstellen und planaren Kontaktieren einer elektronischen Vorrichtung und entsprechend hergestellte Vorrichtung A method for producing and contacting a planar electronic device and device made according to
09/06/2007DE102006009721A1 Semiconductor memory device production, involves forming nano-wire, arranging capacitor dielectric partially on capacitor electrode and arranging another capacitor electrode partially on capacitor dielectric
09/06/2007DE102006009460A1 Process device used in production of integrated circuits comprises process chamber, holder within chamber for holding substrate, radiation source, radiation detector and control and evaluation unit
09/06/2007DE102006009394A1 Wafer treatment involves presenting components during thinning of wafer, separation of components and intermediate production steps, where front of wafer is coated with layer or layer system comprising interface and carrier layer