Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2007
11/20/2007US7297626 Process for nickel silicide Ohmic contacts to n-SiC
11/20/2007US7297625 Group III-V crystal and manufacturing method thereof
11/20/2007US7297624 Semiconductor device and method for fabricating the same
11/20/2007US7297623 Etch stop layer in poly-metal structures
11/20/2007US7297622 Wiring method
11/20/2007US7297621 Flexible carbon-based ohmic contacts for organic transistors
11/20/2007US7297620 Method of forming an oxide layer including increasing the temperature during oxidation
11/20/2007US7297619 System and method for making nanoparticles using atmospheric-pressure plasma microreactor
11/20/2007US7297618 Fully silicided gate electrodes and method of making the same
11/20/2007US7297617 Method for controlling diffusion in semiconductor regions
11/20/2007US7297616 Methods, photoresists and substrates for ion-implant lithography
11/20/2007US7297615 Si nanowire substrate, method of manufacturing the same, and method of manufacturing thin film transistor using the same
11/20/2007US7297614 Method for fabricating circuitry component
11/20/2007US7297613 Method of fabricating and integrating high quality decoupling capacitors
11/20/2007US7297612 Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes
11/20/2007US7297611 Method for producing thin layers of semiconductor material from a donor wafer
11/20/2007US7297610 Method of segmenting a wafer
11/20/2007US7297609 Method for fabricating semiconductor device
11/20/2007US7297608 Method for controlling properties of conformal silica nanolaminates formed by rapid vapor deposition
11/20/2007US7297607 Device and method of performing a seasoning process for a semiconductor device manufacturing apparatus
11/20/2007US7297606 Metal-oxide-semiconductor device including a buried lightly-doped drain region
11/20/2007US7297605 Source/drain extension implant process for use with short time anneals
11/20/2007US7297604 Semiconductor device having dual isolation structure and method of fabricating the same
11/20/2007US7297603 Bi-directional transistor and method therefor
11/20/2007US7297602 Conductive metal oxide gate ferroelectric memory transistor
11/20/2007US7297601 Method for reduced N+ diffusion in strained Si on SiGe substrate
11/20/2007US7297600 Methods of forming fin field effect transistors using oxidation barrier layers
11/20/2007US7297599 Method of fabricating semiconductor device
11/20/2007US7297598 Process for erase improvement in a non-volatile memory device
11/20/2007US7297597 Method for simultaneously fabricating ONO-type memory cell, and gate dielectrics for associated high voltage write transistors and gate dielectrics for low voltage logic transistors by using ISSG
11/20/2007US7297596 Method of manufacturing a semiconductor device having a switching function
11/20/2007US7297595 Non-volatile memory device and fabricating method thereof
11/20/2007US7297594 Non-volatile semiconductor memory device and method of manufacturing the same
11/20/2007US7297593 Method of manufacturing a floating gate of a flash memory device
11/20/2007US7297592 Semiconductor memory with data retention liner
11/20/2007US7297591 Method for manufacturing capacitor of semiconductor device
11/20/2007US7297590 Method for fabricating an integrated pin diode and associated circuit arrangement
11/20/2007US7297589 Transistor device and method
11/20/2007US7297588 Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities and a process for forming the same
11/20/2007US7297587 Composite gate structure in an integrated circuit
11/20/2007US7297586 Gate dielectric and metal gate integration
11/20/2007US7297585 Method of manufacturing semiconductor device having impurity region under isolation region
11/20/2007US7297584 Methods of fabricating semiconductor devices having a dual stress liner
11/20/2007US7297583 Method of making strained channel CMOS transistors having lattice-mismatched epitaxial
11/20/2007US7297582 Method of forming high voltage N-LDMOS transistors having shallow trench isolation region with drain extensions
11/20/2007US7297581 SRAM formation using shadow implantation
11/20/2007US7297580 Methods of fabricating transistors having buried p-type layers beneath the source region
11/20/2007US7297579 Semiconductor device and manufacturing method thereof
11/20/2007US7297578 Method for producing a field effect transistor
11/20/2007US7297577 SOI SRAM device structure with increased W and full depletion
11/20/2007US7297576 Method for fabricating thin film transistor (TFT) display
11/20/2007US7297575 System semiconductor device and method of manufacturing the same
11/20/2007US7297574 Multi-chip device and method for producing a multi-chip device
11/20/2007US7297571 Electrostatically actuated low response time power commutation micro-switches
11/20/2007US7297569 Semiconductor devices with reduced active region defects and unique contacting schemes
11/20/2007US7297568 Three-dimensional structural body composed of silicon fine wire, its manufacturing method, and device using same
11/20/2007US7297567 Method for singulating a released microelectromechanical system wafer
11/20/2007US7297566 Method for producing a display unit
11/20/2007US7297564 Fabrication of vertical sidewalls on (110) silicon substrates for use in Si/SiGe photodetectors
11/20/2007US7297563 Method of making contact pin card system
11/20/2007US7297562 Circuit-on-foil process for manufacturing a laminated semiconductor package substrate having embedded conductive patterns
11/20/2007US7297561 Pattern for improved visual inspection of semiconductor devices
11/20/2007US7297560 Method and apparatus for detecting endpoint
11/20/2007US7297559 Method of fabricating memory and memory
11/20/2007US7297558 Method of manufacturing semiconductor device
11/20/2007US7297557 Method for chemically bonding Langmuir-Blodgett films to substrates
11/20/2007US7297468 Applying photosensitive resin; development, etching, transferring patern
11/20/2007US7297466 Method of forming a photoresist pattern and method for patterning a layer using a photoresist
11/20/2007US7297463 photosensitive polymer without a footing phenomenon even if there is a post exposure delay between an exposure process and a post-exposure-bake process
11/20/2007US7297461 An acid- dissociable group-containing polysiloxane and a photoacid generator containing a trifluoromethane sulfonic acid or other fluoroalkyl sulfonic acid compounds
11/20/2007US7297412 Fabrication of stacked microelectronic devices
11/20/2007US7297361 In-line deposition processes for circuit fabrication
11/20/2007US7297360 Insulation film
11/20/2007US7297315 Recovering copper , manganese; precipitation in acidity solution
11/20/2007US7297287 Method and apparatus for endpoint detection using partial least squares
11/20/2007US7297286 Methods for resist stripping and other processes for cleaning surfaces substantially free of contaminants
11/20/2007US7297239 Method and apparatus for the electrochemical deposition and planarization of a material on a workpiece surface
11/20/2007US7297210 Plating apparatus
11/20/2007US7296777 Acceleration clamp assist
11/20/2007US7296727 Apparatus and method for mounting electronic components
11/20/2007US7296534 Hybrid ball-lock attachment apparatus
11/20/2007US7296533 Radial antenna and plasma device using it
11/20/2007US7296430 Cooling air flow control valve for burn-in system
11/20/2007CA2480117C Spinel substrate and heteroepitaxial growth of iii-v materials thereon
11/15/2007WO2007131119A1 Semiconductor device having a semiconductor-on-insulator configuration and a superlattice and associated methods
11/15/2007WO2007131057A2 Vacuum processing chamber suitable for etching high aspect ratio features and components of same
11/15/2007WO2007131051A1 Method for fabricating a gate dielectric of a field effect transistor
11/15/2007WO2007131046A2 Dielectric trenches, nickel/tantalum oxide structures, and chemical mechanical polishing techniques
11/15/2007WO2007130986A1 Method and apparatus for laser processing
11/15/2007WO2007130938A2 Semiconductor package-on-package system including integrated passive components
11/15/2007WO2007130925A2 Body-tied mosfet device with strained active area
11/15/2007WO2007130795A2 Laminated solar concentrating photovoltaic device
11/15/2007WO2007130790A2 Process condition measuring device with shielding
11/15/2007WO2007130731A2 Barrier for use in 3-d integration of circuits
11/15/2007WO2007130729A2 Method of forming a semiconductor device and structure thereof
11/15/2007WO2007130728A2 Electronic device including semiconductor islands of different thicknesses over an insulating layer and a process of forming the same
11/15/2007WO2007130710A1 Copper electrodeposition in microelectronics
11/15/2007WO2007130708A1 Double side wafer grinder and methods for assessing workpiece nanotopology
11/15/2007WO2007130517A2 Extended probe tips
11/15/2007WO2007130452A1 Removing barnier layer using an electron polishing process
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