Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2007
11/22/2007US20070269968 Semiconductor devices including self aligned refractory contacts and methods of fabricating the same
11/22/2007US20070269967 Manufacturing method of semiconductor device
11/22/2007US20070269966 Methods and apparatus for fabricating semiconductor devices having reduced implant contamination and related devices
11/22/2007US20070269965 Indium Nitride Layer production
11/22/2007US20070269964 Semiconductor-on-diamond devices and associated methods
11/22/2007US20070269963 STRAINED HOT (HYBRID ORIENTATION TECHNOLOGY) MOSFETs
11/22/2007US20070269962 Surface protection film peeling method and surface protection film peeling device
11/22/2007US20070269961 Semiconductor wafer and method for making the same
11/22/2007US20070269960 Fabrication of substrates with a useful layer of monocrystalline semiconductor material
11/22/2007US20070269959 Method of aligning mask layers to buried features
11/22/2007US20070269958 Methods for filling trenches in a semiconductor material
11/22/2007US20070269957 Methods of fabricating semiconductor devices having isolation regions formed from annealed oxygen ion implanted regions
11/22/2007US20070269956 Sealants for metal interconnect protection in microelectronic devices having air gap interconnect structures
11/22/2007US20070269955 Semiconductor device and method for manufacturing same
11/22/2007US20070269954 Semiconductor device including a capacitor having reduced leakage current
11/22/2007US20070269953 Method for the Production of a Bipolar Transistor Comprising an Improved Base Terminal
11/22/2007US20070269952 Method of fabricating a transistor structure
11/22/2007US20070269951 Low Stress Sacrificial Cap Layer
11/22/2007US20070269950 Double gate isolation
11/22/2007US20070269949 Method of fabricating a semiconductor device with a trench isolation structure and resulting semiconductor device
11/22/2007US20070269948 Non-volatile memory array and method of fabricating the same
11/22/2007US20070269947 Method for manufacturing NAND flash memory
11/22/2007US20070269946 Dynamic random access memory and fabrication method thereof
11/22/2007US20070269945 Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator cmos devices
11/22/2007US20070269944 CMOS image sensor
11/22/2007US20070269943 Non-volatile memory and method of fabricating the same
11/22/2007US20070269942 Dual stress liner
11/22/2007US20070269941 Method of forming semiconductor device having a dopant-doped region
11/22/2007US20070269940 Thin film transistor and fabrication method thereof
11/22/2007US20070269939 Flat panel display and method of fabricating the same
11/22/2007US20070269938 Stacked film patterning method and gate electrode forming method
11/22/2007US20070269937 Thin-film transistor and fabrication method thereof
11/22/2007US20070269936 Method of manufacturing lcd apparatus by using halftone exposure method
11/22/2007US20070269935 Fabrication of conductive micro traces using a deform and selective removal process
11/22/2007US20070269934 System and method for providing access to an encapsulated device
11/22/2007US20070269933 Integrated circuit encapsulation and method therefor
11/22/2007US20070269932 Semiconductor Device Having Post-Mold Nickel/Palladium/Gold Plated Leads
11/22/2007US20070269931 Wafer level package and method of fabricating the same
11/22/2007US20070269930 Methodology to control underfill fillet size, flow-out and bleed in flip chips (FC), chip scale packages (CSP) and ball grid arrays (BGA)
11/22/2007US20070269929 Method of reducing stress on a semiconductor die with a distributed plating pattern
11/22/2007US20070269928 Temporary chip attach using injection molded solder
11/22/2007US20070269927 Method for producing an optoelectronic device with patterned-metallized package body and method for the patterned metalization of a plastic-containing body
11/22/2007US20070269926 Method and apparatus for forming an electrical connection to a semiconductor substrate
11/22/2007US20070269925 Process For Preparing A Semiconductor Light-Emitting Device For Mounting
11/22/2007US20070269924 Patterning nanowires on surfaces for fabricating nanoscale electronic devices
11/22/2007US20070269923 Semiconductor electrode containing phosphate and solar cell using the same
11/22/2007US20070269922 Fingerprint detection device and method of its manufacture, and apparatus for forming a protective film
11/22/2007US20070269921 Method and apparatus for microjoining dissimilar materials
11/22/2007US20070269920 Method of making dimple structure for prevention of mems device stiction
11/22/2007US20070269919 Controlling overspray coating in semiconductor devices
11/22/2007US20070269918 Method of manufacturing nitride-based semiconductor light emitting device
11/22/2007US20070269916 Organic light emitting diode display and manufacturing method
11/22/2007US20070269915 LED devices incorporating moisture-resistant seals and having ceramic substrates
11/22/2007US20070269914 Apparatus For Aligning Microchips On Substrate And Method For The Same
11/22/2007US20070269913 Method of fabricating light emitting diode
11/22/2007US20070269912 In line test circuit and method for determining interconnect electrical properties and integerated circuit incorporating the same
11/22/2007US20070269911 Memory-Module Manufacturing Method with Memory-Chip Burn-In and Full Functional Testing Delayed Until Module Burn-In
11/22/2007US20070269910 Wafer Tilt Detection Apparatus and Method
11/22/2007US20070269909 Method for processing an integrated circuit
11/22/2007US20070269908 Method for in-line controlling hybrid chemical mechanical polishing process
11/22/2007US20070269907 Novel conductor layout technique to reduce stress-induced void formations
11/22/2007US20070269751 Immersion Liquid for Liquid Immersion Lithography Process and Method for Forming Resist Pattern Using Such Immersion Liquid
11/22/2007US20070269735 Radiation-Sensitive Resin Composition
11/22/2007US20070269734 Uper Layer Film Forming Composition for Liquid Immersion and Method of Forming Photoresist Pattern
11/22/2007US20070269723 Near-zero phase shift
11/22/2007US20070269663 Method for fabricating a substrate with useful layer on high resistivity support
11/22/2007US20070269294 Substrate Holding Device, Exposure Apparatus, and Device Manufacturing Method
11/22/2007US20070269293 Substrate carrier and facility interface and apparatus including same
11/22/2007US20070269263 Fastener System
11/22/2007US20070269103 Stereoscopic three-dimensional metrology system and method
11/22/2007US20070269101 Pattern inspection method and apparatus
11/22/2007US20070268628 Abs through aggressive stitching
11/22/2007US20070268471 Lithographic apparatus and device manufacturing method
11/22/2007US20070268040 Logic circuit system and method of changing operating voltage of a programmable logic circuit
11/22/2007US20070267955 Activation Effect on Carbon Nanotubes
11/22/2007US20070267761 Semiconductor device and method of designing the semiconductor device
11/22/2007US20070267752 Semiconductor Device having Pad Structure for Preventing and Buffering Stress of Silicon Nitride Film
11/22/2007US20070267749 Metallization layer for a power semiconductor device
11/22/2007US20070267745 Semiconductor device including electrically conductive bump and method of manufacturing the same
11/22/2007US20070267744 Manufacturing a bump electrode with roughened face
11/22/2007US20070267738 Stack-type semiconductor device having cooling path on its bottom surface
11/22/2007US20070267732 Circuit card module and method for fabricating the same
11/22/2007US20070267731 Integrated circuit package system with different mold locking features
11/22/2007US20070267725 Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package
11/22/2007US20070267724 Integrated circuit having stress tuning layer and methods of manufacturing same
11/22/2007US20070267723 Double-sided integrated circuit chips
11/22/2007US20070267714 Top layers of metal for high performance IC's
11/22/2007US20070267709 Magnetic sensor having vertical hall device
11/22/2007US20070267705 Semiconductor integrated circuit device having MIM capacitor and method of fabricating the same
11/22/2007US20070267704 Method of fabricating thin film transistor
11/22/2007US20070267698 Dual wired integrated circuit chips
11/22/2007US20070267695 Silicon-on-insulator structures and methods of forming same
11/22/2007US20070267688 SONOS memory device having nano-sized trap elements
11/22/2007US20070267685 Nonvolatile semiconductor memory and method of manufacturing the same
11/22/2007US20070267681 Semiconductor device and method of manufacturing the same
11/22/2007US20070267679 Nonvolatile memory devices including floating gates formed of silicon nano-crystals and methods of manufacturing the same
11/22/2007US20070267676 Fin field effect transistor and method for forming the same
11/22/2007US20070267675 Nonvolatile memory devices including oxygen-deficient metal oxide layers and methods of manufacturing the same
11/22/2007US20070267672 Semiconductor device and method for manufacturing same
11/22/2007US20070267668 Semiconductor constructions, DRAM arrays, and methods of forming semiconductor constructions
1 ... 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 ... 6590