Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2007
11/29/2007WO2007135620A1 Method of increasing the quality factor of an inductor in a semiconductor device
11/29/2007WO2007135514A2 Liquid ring pumping and reclamation systems in a processing environment
11/29/2007WO2007135513A1 Systems and methods for managing fluids in a processing environment using a liquid ring pump and reclamation system
11/29/2007WO2007135502A1 Systems and methods for reclaiming process fluids in a processing environment
11/29/2007WO2007135347A1 Method and device for removing pollution from a confined environment
11/29/2007WO2007135214A1 Flexible micro/nanofluidic devices
11/29/2007WO2007134905A1 Symmetrical mim capacitor design
11/29/2007WO2007134903A1 High yield high density on-chip capacitor design
11/29/2007WO2007134751A1 Non-volatile memory cell of a circuit integrated in a semiconductor chip, method for producing it, and use of a non-volatile memory cell
11/29/2007WO2007134581A1 Electrically conducting connection with insulating connection medium
11/29/2007WO2007117718A3 Simplified pitch doubling process flow
11/29/2007WO2007112066A3 Lattice-mismatched semiconductor structures and related methods for device fabrication
11/29/2007WO2007110507A3 Process for fabricating a field-effect transistor with self-aligned gates
11/29/2007WO2007109432A3 Methods and apparatus for electroprocessing with recessed bias contact
11/29/2007WO2007106502A3 Thin silicon or germanium sheets and photovoltaics formed from thin sheets
11/29/2007WO2007098459A3 Semiconductor device with nitrogen containing oxide layer
11/29/2007WO2007092856A3 Copper interconnect wiring and method and apparatus for forming thereof
11/29/2007WO2007092749A3 Semiconductive device fabricated using a two step approach to silicide a gate and source/drains
11/29/2007WO2007089949A3 Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes
11/29/2007WO2007087021A3 Wafer encapsulated microelectromechanical structure and method of manufacturing same
11/29/2007WO2007075840A3 Extended mainframe designs for semiconductor device manufacturing equipment
11/29/2007WO2007072405B1 Semiconductor device with recessed field plate and method of manufacturing the same
11/29/2007WO2007070775A3 Integrated circuit with antireflective coating
11/29/2007WO2007070321A3 System and method for the manufacture of semiconductor devices by the implantation of carbon clusters
11/29/2007WO2007047369A3 Method for fabricating a gate dielectric of a field effect transistor
11/29/2007WO2007024332A3 An apparatus and method for non-contact assessment of a constituent in semiconductor substrates
11/29/2007WO2007001709A3 Improved manufacturing method for two-step post nitridation annealing of plasma nitrided gate dielectric
11/29/2007WO2006135420A3 Method for simultaneous fabrication of a nanocrystal and non-nanocrystal device
11/29/2007WO2006132878A3 Substrate support
11/29/2007WO2006119380A3 Silicon wafer having through-wafer vias
11/29/2007WO2006105156A8 High speed substrate aligner apparatus
11/29/2007WO2006078298A3 Spin-coatable liquid for formation of high purity nanotube films
11/29/2007WO2006039133A3 Cluster tool process chamber having integrated high pressure and vacuum chambers
11/29/2007WO2005055280A3 Wafer container and door with cam latching mechanism
11/29/2007WO2003071605A3 Semiconductor devices formed of iii-nitride compounds, lithium-niobate-tantalate, and silicon carbide
11/29/2007WO2002096799A3 Silicon subnitride method for production and use of said subnitride
11/29/2007US20070276620 Method of correcting coordinates, and defect review apparatus
11/29/2007US20070276533 Method For Detecting Transfer Shift Of Transfer Mechanism And Semiconductor Processing Equipment
11/29/2007US20070276530 Methods and apparatus for material control system interface
11/29/2007US20070276529 Methods and apparatus for transferring a substrate carrier within an electronic device manufacturing facility
11/29/2007US20070276528 Management system of semiconductor fabrication apparatus, abnormality factor extraction method of semiconductor fabrication apparatus, and management method of the same
11/29/2007US20070275639 Workpiece centering apparatus and method of centering workpiece
11/29/2007US20070275570 Heat Treatment Apparatus
11/29/2007US20070275569 Methods and apparatus for e-beam treatment used to fabricate integrated circuit devices
11/29/2007US20070275568 UV stabilizer, Beige pigment, anti-block, low density polyethylene, polypropylene, and anti-slip butylene-ethylene-styrene block terpolymer; KRATON.RTM. MD6649; low in cost and helps prevent water from penetrating the primary roofing material; anti-skid surface upon which an individual may safely walk
11/29/2007US20070275567 Forming a dielectric layer of oxides of Zirconium, tin, and Titanium film; minimal reactions with a silicon substrate or other structures during processing; thermodynamic stability
11/29/2007US20070275566 Method of producing semiconductor substrate
11/29/2007US20070275565 Full removal of dual damascene metal level
11/29/2007US20070275564 Etching method and storage medium
11/29/2007US20070275563 Mask forming and implanting methods using implant stopping layer and mask so formed
11/29/2007US20070275562 Apparatus and method for treating substrate, and injection head used in the apparatus
11/29/2007US20070275561 Gas switching during an etch process to modulate the characteristics of the etch
11/29/2007US20070275560 Method of manufacturing semiconductor device
11/29/2007US20070275559 Method of manufacturing flash memory device
11/29/2007US20070275558 Method for manufacuturing semiconductor device
11/29/2007US20070275557 Formation of oxidation-resistant seed layer for interconnect applications
11/29/2007US20070275556 Fabrication Method
11/29/2007US20070275555 Method of forming an electrical contact in a semiconductor device using an improved self-aligned contact (SAC) process
11/29/2007US20070275554 Semiconductor device with interconnection structure for reducing stress migration
11/29/2007US20070275553 Method for manufacturing semiconductor device
11/29/2007US20070275552 Structure for reducing lateral fringe capacitance in semiconductor devices and method of forming the same
11/29/2007US20070275551 Shapes-based migration of aluminum designs to copper damascene
11/29/2007US20070275550 Barrier layer for fine-pitch mask-based substrate bumping
11/29/2007US20070275549 Contact surrounded by passivation and polymide and method therefor
11/29/2007US20070275548 Method and structure for reducing contact resistance between silicide contact and overlying metallization
11/29/2007US20070275547 Integrated circuit structure and manufacturing method thereof
11/29/2007US20070275545 Higher selectivity, method for passivating short circuit current paths in semiconductor devices
11/29/2007US20070275544 Fabrication method of semiconductor device
11/29/2007US20070275543 Manufacturing method of a semiconductor device
11/29/2007US20070275542 Substrate separation method and liquid ejecting head production method using the substrate separation method
11/29/2007US20070275541 Back side wafer dicing
11/29/2007US20070275540 Backside via formation prior to die attachment
11/29/2007US20070275539 Method of stimulating die circuitry and structure therefor
11/29/2007US20070275538 Method with High Gapfill Capability for Semiconductor Devices
11/29/2007US20070275537 Formation of improved soi substrates using bulk semiconductor wafers
11/29/2007US20070275536 Mim capacitor
11/29/2007US20070275535 Bipolar transistor with self-aligned retrograde extrinsic base implant profile and self-aligned silicide
11/29/2007US20070275534 Varied impurity profile region formation for varying breakdown voltage of devices
11/29/2007US20070275533 Semiconductor device structures with backside contacts for improved heat dissipation and reduced parasitic resistance
11/29/2007US20070275532 Optimized deep source/drain junctions with thin poly gate in a field effect transistor
11/29/2007US20070275531 Method of manufacturing flash memory device
11/29/2007US20070275530 Semiconductor structure and fabricating method thereof
11/29/2007US20070275529 Semiconductor device manufacturing method
11/29/2007US20070275528 Method of manufacturing semiconductor device
11/29/2007US20070275527 Self-aligned trench field effect transistors with regrown gates and bipolar junction transistors with regrown base contact regions and methods of making
11/29/2007US20070275526 Methods of programming memory cells using manipulation of oxygen vacancies
11/29/2007US20070275525 Capacitive substrate and method of making same
11/29/2007US20070275524 Semiconductor device fabrication method
11/29/2007US20070275523 Trench-capacitor dram device and manufacture method thereof
11/29/2007US20070275522 Method to enhance cmos transistor performance by inducing strain in the gate and channel
11/29/2007US20070275521 Method of manufacturing hollow micro-needle structures
11/29/2007US20070275520 Method of manufacturing semiconductor device
11/29/2007US20070275519 Method of manufacturing non-volatile memory device
11/29/2007US20070275518 Pixel structure and fabrication method thereof
11/29/2007US20070275517 Dual poly deposition and through gate oxide implants
11/29/2007US20070275516 Manufacturing Method of Semiconductor Device
11/29/2007US20070275515 Deep buried channel junction field effect transistor (DBCJFET)
11/29/2007US20070275514 Semiconductor device and method of manufacturing same
11/29/2007US20070275513 Formation of shallow siGe conduction channel
11/29/2007US20070275512 Method for manufacturing thin film transistor substrate using maskless exposing device
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