Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2008
08/28/2008WO2008101713A2 High throughput sem tool
08/28/2008WO2008101699A2 Method for laser supported bonding substrates bonded thus and use thereof
08/28/2008WO2008101626A1 Method for producing (al, ga)inn crystals
08/28/2008WO2008101625A1 Method for producing (al,ga)n crystals
08/28/2008WO2008086348A3 Semiconductor device and method of manufacturing the same
08/28/2008WO2008085686A3 Structure and method for mobility enhanced mosfets with unalloyed silicide
08/28/2008WO2008079691A3 Semiconductor die with separation trench etch and passivation
08/28/2008WO2008078185A3 Antireflective coating compositions
08/28/2008WO2008076152A3 Nanoscale floating gate and methods of formation
08/28/2008WO2008073977A3 Method to remove circuit patterns from a wafer
08/28/2008WO2008073767A3 Methods of filling a set of interstitial spaces of a nanoparticle thin film with a dielectric material
08/28/2008WO2008060244A8 Net block assembly
08/28/2008WO2008054332A8 A unit lifter assembly
08/28/2008WO2008048710A3 Nanometer-scale sharpening of conductor tips
08/28/2008WO2008039372B1 Assembling and applying nano-electro-mechanical systems
08/28/2008WO2008038158A3 Formation of through-wafer electrical interconnections and other structures using an etch stop layer
08/28/2008WO2008027794A3 Spin coater with optical controls
08/28/2008WO2007149581A3 Buried channel mosfet using iii-v compound semiconductors and high k gate dielectrics
08/28/2008WO2007140377A3 A novel deposition-plasma cure cycle process to enhance film quality of silicon dioxide
08/28/2008WO2007123616A3 Organic barc etch process capable of use in the formation of low k dual damascene integrated circuits
08/28/2008WO2007056689A3 Nitrogen based implants for defect reduction in strained silicon
08/28/2008WO2006089072A3 Generation and applications of negative dielectric constant material
08/28/2008WO2006076298A3 Trench schottky barrier diode with differential oxide thickness
08/28/2008US20080209386 Method for predicting resist pattern shape, computer readable medium storing program for predicting resist pattern shape, and computer for predicting resist pattern shape
08/28/2008US20080209381 Shallow trench isolation dummy pattern and layout method using the same
08/28/2008US20080209364 Method for storing multiple levels of design data in a common database
08/28/2008US20080209303 Error Detection/Correction Method
08/28/2008US20080208658 Method and system for estimating supply impact on a firm under a global crisis
08/28/2008US20080208386 Semiconductor manufacturing system, controller, semiconductor manufacturing system control method, and processing liquid collection method
08/28/2008US20080208385 Semiconductor Manufacturing Apparatus, Method of Detecting Abnormality, Identifying Cause of Abnormality, or Predicting Abnormality in the Semiconductor Manufacturing Apparatus, and Storage Medium Storing Computer Program for Performing the Method
08/28/2008US20080207159 Radio frequency circuit with integrated on-chip radio frequency inductive signal coupler
08/28/2008US20080207008 Microwave hybrid and plasma rapid thermal processing of semiconductor wafers
08/28/2008US20080207007 Plasma Enhanced Cyclic Chemical Vapor Deposition of Silicon-Containing Films
08/28/2008US20080207006 Process for fabricating an integrated circuit
08/28/2008US20080207005 Wafer Cleaning After Via-Etching
08/28/2008US20080207004 Method of Forming a Semiconductor Structure
08/28/2008US20080207003 Production method of semiconductor apparatus
08/28/2008US20080207002 Method of removing graphitic and/or fluorinated organic layers from the surface of a chip passivation layer having si-containing compounds
08/28/2008US20080207001 Pulsed Etching Cooling
08/28/2008US20080207000 Method of making high-aspect ratio contact hole
08/28/2008US20080206999 Method for wet etching while forming interconnect trench in insulating film
08/28/2008US20080206998 Semiconductor fabrication apparatuses to perform semiconductor etching and deposition processes and methods of forming semiconductor device using the same
08/28/2008US20080206997 Method for Manufacturing Insulating Film and Method for Manufacturing Semiconductor Device
08/28/2008US20080206996 Sidewall image transfer processes for forming multiple line-widths
08/28/2008US20080206995 Metal-polishing liquid and polishing method therewith
08/28/2008US20080206994 Method of reducing non-uniformities during chemical mechanical polishing of excess metal in a metallization level of microstructure devices
08/28/2008US20080206993 Using Spectra to Determine Polishing Endpoints
08/28/2008US20080206992 Method for manufacturing high flatness silicon wafer
08/28/2008US20080206991 Methods of forming transistor contacts and via openings
08/28/2008US20080206990 Methods For Fabricating Semiconductor Components With Conductive Interconnects
08/28/2008US20080206989 Method for Producing Vertical Electrical Contact Connections in Semiconductor Wafers
08/28/2008US20080206988 Formation of fully silicided gate with oxide barrier on the source/drain silicide regions
08/28/2008US20080206987 Process for tungsten nitride deposition by a temperature controlled lid assembly
08/28/2008US20080206986 Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime
08/28/2008US20080206985 Method of fabricating a semiconductor device
08/28/2008US20080206984 Conductive via formation utilizing electroplating
08/28/2008US20080206983 Method of manufacturing photoelectric conversion device
08/28/2008US20080206982 Interconnect structures with a metal nitride diffusion barrier containing ruthenium and method of forming
08/28/2008US20080206981 Semiconductor device and manufacturing method therefor
08/28/2008US20080206980 Method for manufacturing semiconductor device, and method and structure for implementing semiconductor device
08/28/2008US20080206979 Interconnections for flip-chip using lead-free solders and having reaction barrier layers
08/28/2008US20080206978 Electronic fuses in semiconductor integrated circuits
08/28/2008US20080206977 Methods of forming wiring to transistor and related transistor
08/28/2008US20080206976 Semiconductor device and method of manufacturing the same
08/28/2008US20080206975 Method of manufacturing a nonvolatile semiconductor memory device, and a nonvolatile semiconductor memory device
08/28/2008US20080206974 Fabrication of semiconductor device having composite contact
08/28/2008US20080206973 Process method to optimize fully silicided gate (FUSI) thru PAI implant
08/28/2008US20080206972 Doped nanoparticle-based semiconductor junction
08/28/2008US20080206971 Divergent charged particle implantation for improved transistor symmetry
08/28/2008US20080206970 Production Of Polycrystalline Silicon
08/28/2008US20080206969 Laser Optical Apparatus
08/28/2008US20080206968 Manufacturing method of semiconductor device
08/28/2008US20080206967 Method for forming semiconductor device
08/28/2008US20080206966 Quantum dots nucleation layer of lattice mismatched epitaxy
08/28/2008US20080206965 STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY
08/28/2008US20080206964 Carbon Nanotube Transistor Process with Transferred Carbon Nanotubes
08/28/2008US20080206963 Cleaving process to fabricate multilayered substrates using low implantation doses
08/28/2008US20080206962 Method and structure for thick layer transfer using a linear accelerator
08/28/2008US20080206961 Semiconductor device and semiconductor substrate
08/28/2008US20080206960 Reworkable chip stack
08/28/2008US20080206959 Peeling method
08/28/2008US20080206958 ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXIAL COMPRESSIVE STRAIN
08/28/2008US20080206957 Method of Forming Isolation Layer of Semiconductor Memory Device
08/28/2008US20080206956 Semiconductor device fabrication method
08/28/2008US20080206955 Method of Forming an Isolation Film in a Semiconductor Device
08/28/2008US20080206954 Methods of reducing impurity concentration in isolating films in semiconductor devices
08/28/2008US20080206953 Method for manufacturing semiconductor device
08/28/2008US20080206952 Silicon Substrate Processing Method
08/28/2008US20080206951 High performance field effect transistors on soi substrate with stress-inducing material as buried insulator and methods
08/28/2008US20080206950 Methods of forming a plurality of capacitors
08/28/2008US20080206949 Apparatus for forming conductor, method for forming conductor, and method for manufacturing semiconductor device
08/28/2008US20080206948 Semiconductor device and method of fabricating the same
08/28/2008US20080206947 Method of manufacturing semiconductor device
08/28/2008US20080206946 Memory and method of fabricating the same
08/28/2008US20080206945 Process for forming differential spaces in electronics device integrated on a semiconductor substrate
08/28/2008US20080206944 Method for fabricating trench DMOS transistors and schottky elements
08/28/2008US20080206943 Method of forming strained cmos transistor
08/28/2008US20080206942 Method for fabricating strained-silicon metal-oxide semiconductor transistors
08/28/2008US20080206941 Method for manufacturing sic semiconductor device
08/28/2008US20080206940 Forming a semiconductor device having epitaxially grown source and drain regions
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