Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
04/2012
04/05/2012WO2012041033A1 Method for forming metal interconnection structure, through hole between metallization layers and interconnect metallization lines
04/05/2012WO2012040873A1 Singulation of ic packages
04/05/2012WO2012021370A4 Enhanced wafer carrier
04/05/2012WO2012018448A3 Plasma processing chamber with dual axial gas injection and exhaust
04/05/2012WO2012018368A3 Parasitic plasma prevention in plasma processing chambers
04/05/2012WO2012014092A3 Apparatus and method for three dimensional inspection of wafer saw marks
04/05/2012WO2012009308A3 Methods for forming barrier/seed layers for copper interconnect structures
04/05/2012WO2012009257A3 P-gan fabrication process utilizing a dedicated chamber and method of minimizing magnesium redistribution for sharper decay profile
04/05/2012WO2012006063A3 Microelectronic package and method of manufacturing same
04/05/2012WO2012006029A3 System and method of semiconductor manufacturing with energy recovery
04/05/2012WO2012006019A3 Customizable dispense system with smart controller
04/05/2012WO2012005939A3 Closed-loop control of cmp slurry flow
04/05/2012WO2012005890A3 Substrate support for use with multi-zonal heating sources
04/05/2012WO2012003368A3 Transistor circuits for detection and measurement of chemical reactions and compounds
04/05/2012WO2011163344A3 Low voltage pnpn protection device
04/05/2012WO2011163037A3 Plasma-enhanced chemical vapor deposition of crystalline germanium
04/05/2012WO2011160105A3 Endpoint determination for capillary-assisted flow control
04/05/2012WO2011160041A3 High voltage transistor using diluted drain
04/05/2012WO2011159690A3 Multiple precursor showerhead with by-pass ports
04/05/2012WO2011159625A3 Advanced process control optimization
04/05/2012WO2011159536A3 A splicing technique for fixed abrasives used in chemical mechanical planarization
04/05/2012WO2011159456A3 Optically tuned metalized light to heat conversion layer for wafer support system
04/05/2012WO2011156749A3 Graphene deposition
04/05/2012WO2011156705A3 Selective formation of metallic films on metallic surfaces
04/05/2012WO2011156349A3 Methods for forming interconnect structures
04/05/2012WO2011153420A3 Method of improving film non-uniformity and throughput
04/05/2012WO2011152858A3 Oxide based memory
04/05/2012WO2011149768A3 Self-aligned semiconductor devices with reduced gate-source leakage under reverse bias and methods of making
04/05/2012WO2011149508A3 Apparatus and method for temperature control of a semiconductor substrate support
04/05/2012WO2011146913A3 Germanium antimony telluride materials and devices incorporating same
04/05/2012WO2011146672A3 Apparatuses and methods for scrubbing substrates
04/05/2012WO2011146432A3 Controlled vaporization system and method for surface priming in semiconductor manufacturing
04/05/2012WO2011146108A3 Movable chamber liner plasma confinement screen combination for plasma processing apparatuses
04/05/2012WO2011136959A3 Methods for monitoring processing equipment
04/05/2012WO2011133680A3 Novel dual-tone resist formulations and methods
04/05/2012WO2011133562A3 Methods and apparatus for an induction coil arrangement in a plasma processing system
04/05/2012WO2011130693A3 Method for fabricating through-substrate microchannels
04/05/2012WO2011122068A9 Contact probe, contact probe connecting body and methods for manufacturing same
04/05/2012WO2011106750A3 Method and apparatus for enhanced lifetime and performance of ion source in an ion implantation system
04/05/2012WO2011103062A3 Reactive site deactivation against vapor deposition
04/05/2012WO2011059961A3 Semiconductor device fabrication using a multiple exposure and block mask approach to reduce design rule violations
04/05/2012WO2003079374A3 Methods for forming articles having very small channels therethrough, and such articles, and methods of using such articles
04/05/2012US20120083139 Memory module and method of manufacturing a memory module
04/05/2012US20120083136 Method and system for modifying patterned photoresist using multi-step ion implantation
04/05/2012US20120083135 Asymmetric rapid thermal annealing to reduce pattern effect
04/05/2012US20120083134 Method of mitigating substrate damage during deposition processes
04/05/2012US20120083133 Amine curing silicon-nitride-hydride films
04/05/2012US20120083132 Method for minimizing defects in a semiconductor substrate due to ion implantation
04/05/2012US20120083131 Method and apparatus for treating silicon substrate
04/05/2012US20120083130 Apparatus and methods for shielding a plasma etcher electrode
04/05/2012US20120083129 Apparatus and methods for focusing plasma
04/05/2012US20120083128 Method for etching high-aspect-ratio features
04/05/2012US20120083127 Method for forming a pattern and a semiconductor device manufacturing method
04/05/2012US20120083126 Method for forming semiconductor device
04/05/2012US20120083125 Chemical Mechanical Planarization With Overburden Mask
04/05/2012US20120083124 Method of Patterning NAND Strings Using Perpendicular SRAF
04/05/2012US20120083123 Chemical Mechanical Planarization Processes For Fabrication of FINFET Devices
04/05/2012US20120083122 Shallow Trench Isolation Chemical Mechanical Planarization
04/05/2012US20120083121 Fabrication of Replacement Metal Gate Devices
04/05/2012US20120083120 Substrate processing apparatus and method of manufacturing a semiconductor device
04/05/2012US20120083119 Semiconductor device and method of manufacturing the same
04/05/2012US20120083118 Methods of evaporating metal onto a semiconductor wafer in a test wafer holder
04/05/2012US20120083117 Method Of Forming Hardened Porous Dielectric Layer And Method Of Fabricating Semiconductor Device Having Hardened Porous Dielectric Layer
04/05/2012US20120083116 Cost-Effective TSV Formation
04/05/2012US20120083115 Method for manufacturing a semiconductor device having an interconnect structure and a reinforcing insulating film
04/05/2012US20120083114 Dimensionally decoupled ball limiting metalurgy
04/05/2012US20120083113 Creation of lead-free solder joint with intermetallics
04/05/2012US20120083112 Method of manufacturing nonvolatile semiconductor memory with backing wirings
04/05/2012US20120083111 Methods of Manufacturing a Semiconductor Device
04/05/2012US20120083110 Method for manufacturing mos transistors with different types of gate stacks
04/05/2012US20120083109 Semiconductor device and method of manufacturing the same
04/05/2012US20120083108 Transistor Level Routing
04/05/2012US20120083107 FinFETs Having Dielectric Punch-Through Stoppers
04/05/2012US20120083106 Method for manufacturing semiconductor structure
04/05/2012US20120083105 Method for boron doping silicon wafers
04/05/2012US20120083104 Methods of forming a floating junction on a solar cell with a particle masking layer
04/05/2012US20120083103 Method for minimizing defects in a semiconductor substrate due to ion implantation
04/05/2012US20120083102 Integrated Shadow Mask/Carrier for Pattern Ion Implantation
04/05/2012US20120083101 Systems and methods for forming semiconductor materials by atomic layer deposition
04/05/2012US20120083100 Thermalizing gas injectors for generating increased precursor gas, material deposition systems including such injectors, and related methods
04/05/2012US20120083099 Printable Semiconductor Structures and Related Methods of Making and Assembling
04/05/2012US20120083098 Method for Manufacturing a Composite Wafer Having a Graphite Core, and Composite Wafer Having a Graphite Core
04/05/2012US20120083097 Methods of Forming a Semiconductor Package Using a Seed Layer and Semiconductor Packages Formed Using the Same
04/05/2012US20120083096 Semiconductor device having a simplified stack and method for manufacturing tehreof
04/05/2012US20120083095 Method of fabricating semiconductor device by thinning hardmask layers on frontside and backside of substrate
04/05/2012US20120083094 Integrated circuit guard rings
04/05/2012US20120083093 Isolation structure for a memory cell using al2o3 dielectric
04/05/2012US20120083092 Structure and method of forming enhanced array device isolation for implanted plate edram
04/05/2012US20120083091 Deep trench electrostatic discharge (esd) protect diode for silicon-on-insulator (soi) devices
04/05/2012US20120083090 Method of fabricating an NMOS transistor
04/05/2012US20120083089 Fabricating method of metal silicide layer, fabricating method of semiconductor device using the same and semiconductor device fabricated using the method
04/05/2012US20120083088 Integrated circuit device with well controlled surface proximity and method of manufacturing same
04/05/2012US20120083087 Method of manufacturing semiconductor device
04/05/2012US20120083086 Semiconductor device and manufacturing method therefor
04/05/2012US20120083085 Method for producing an electrode structure
04/05/2012US20120083084 Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source
04/05/2012US20120083083 Trench metal oxide semiconductor field effect transistor (MOSFET) with low gate to drain coupled charges (Qgd) structures
04/05/2012US20120083082 Method of manufacturing semiconductor device
04/05/2012US20120083081 Method for producing a gate electrode structure
04/05/2012US20120083080 Method for reducing punch-through in a transistor device
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