Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
07/2014
07/08/2014US8773943 Semiconductor device outputting read data in synchronization with clock signal
07/08/2014US8773942 Segmented memory having power-saving mode
07/08/2014US8773941 Method and apparatus for decoding memory
07/08/2014US8773940 Skewed SRAM cell
07/08/2014US8773939 Stacked memory devices with micro channels and memory systems including the same
07/08/2014US8773932 Built-in self-test circuit applied to high speed I/O port
07/08/2014US8773919 Semiconductor device and data processing system
07/03/2014WO2014105537A1 Nonvolatile memory and method with improved i/o interface
07/02/2014CN102209989B 动态实时延迟表征和配置 Dynamic real-time delay characterization and configuration
07/01/2014US8769234 Memory modules and devices supporting configurable data widths
07/01/2014US8767504 Activate signal generating circuit and semiconductor memory device
07/01/2014US8767503 Clock transfer circuit and semiconductor device including the same
07/01/2014US8767502 Semiconductor device verifying signal supplied from outside
07/01/2014US8767501 Self-reconfigurable address decoder for associative index extended caches
07/01/2014US8767500 Buffer circuit and word line driver using the same
07/01/2014US8767499 Semiconductor memory device
07/01/2014US8767494 Far end resistance tracking design with near end pre-charge control for faster recovery time
07/01/2014US8767485 Operation method of a supply voltage generation circuit used for a memory array
07/01/2014US8767480 Semiconductor memory device and method of operating the same
07/01/2014US8767479 Semiconductor memory device and driving method thereof
07/01/2014US8767460 Nonvolatile semiconductor memory device
07/01/2014US8767430 Configurable module and memory subsystem
06/2014
06/26/2014US20140177377 Data signal receiver and method of calibrating a data signal receiver
06/26/2014US20140177376 Memory and memory system including the same
06/26/2014US20140177375 Memory Device with Internal Combination Logic
06/26/2014US20140177358 Address counting circuit and semiconductor apparatus using the same
06/26/2014US20140177346 Apparatus to suppress concurrent read and write word line access of the same memory element in a memory array
06/26/2014US20140177344 Method and apparatus for clock power saving in multiport latch arrays
06/26/2014US20140177324 Single-Port Read Multiple-Port Write Storage Device Using Single-Port Memory Cells
06/26/2014US20140177314 Semiconductor memory devices and semiconductor system having parameters, and methods of testing the same
06/26/2014US20140177311 Memory device structure with decoders in a device level separate from the array level
06/25/2014CN103890853A 具有金属-绝缘体-金属阈值开关的解码器电路 Having a metal - insulator - metal threshold switch decoder circuit
06/25/2014CN102282619B 用以在ddr dram写入期间三态控制未使用数据字节的方法、系统及设备 For the tri-state control during ddr dram unused data byte is written to methods, systems and equipment
06/25/2014CN101894582B 存储数据译码方法,装置以及设备 Storing data decoding method, apparatus, and equipment
06/25/2014CN101388236B 多层存储装置 Multi-tier storage device
06/24/2014US8762654 Selectively scheduling memory accesses in parallel based on access speeds of memory
06/24/2014US8760961 Write command and write data timing circuit and methods for timing the same
06/24/2014US8760960 Semiconductor memory apparatus and data input/output method thereof
06/24/2014US8760959 Memory device and electronic device
06/24/2014US8760958 Methods and apparatus for designing and constructing multi-port memory circuits with voltage assist
06/24/2014US8760957 Non-volatile memory and method having a memory array with a high-speed, short bit-line portion
06/24/2014US8760956 Data processing method and apparatus
06/24/2014US8760946 Method and apparatus for memory access delay training
06/24/2014US8760944 Memory component that samples command/address signals in response to both edges of a clock signal
06/24/2014US8760943 Semiconductor apparatus
06/19/2014US20140169119 Memory system having delay-locked-loop circuit
06/19/2014US20140169118 Address input circuit of semiconductor apparatus
06/19/2014US20140169117 Decoder circuit with reduced current leakage
06/19/2014US20140169073 Semiconductor integrated circuit with thick gate oxide word line driving circuit
06/18/2014CN103871450A Semiconductor memory device and system having redundancy cells
06/18/2014CN103871447A NAND flash memory array, NAND flash memory chip, and methods for accessing, reading and managing NAND flash memory array
06/18/2014CN102265349B Non-binary decoder architecture and control signal logic for reducing circuit complexity
06/18/2014CN101800073B 记忆体阵列以及记忆体装置 Memory array and memory devices
06/17/2014US8755246 Semiconductor memory device and method of setting operation environment therein
06/17/2014US8755245 Decoder control
06/17/2014US8755244 Write contention-free, noise-tolerant multi-port bitcell
06/17/2014US8755239 Read assist circuit for an SRAM
06/17/2014US8755217 Semiconductor memory device
06/12/2014US20140160876 Address bit remapping scheme to reduce access granularity of dram accesses
06/12/2014US20140160875 Row address decoding block for non-volatile memories and methods for decoding pre-decoded address information
06/12/2014DE102013018135A1 Adressenbit-Wiederabbildungsschema zur Reduzierung einer Zugriffsauflösung von DRAM-Zugriffen Address bit-remapping scheme to reduce an access resolution of DRAM accesses
06/10/2014US8750026 Integrated circuits with asymmetric and stacked transistors
06/05/2014US20140153349 Simultaneous Two/Dual Port Access on 6T SRAM
06/05/2014DE102013113415A1 Sequenziell-Zugriffsspeicher mit Haupt-Neben-Speicher mit Haupt-Neben-Signalspeicherpaaren und Verfahren zum Betreiben Sequential access memory with the main memory with sub-main-slave latch pairs and methods of operating
06/05/2014DE102007030973B4 Speichervorrichtung und Verfahren zur Betätigung einer Speichervorrichtung, insbesondere eines DRAM Memory device and method of operating a memory device, in particular a DRAM
06/04/2014CN103843066A Pseudo-inverter circuit with multiple independent gate transistors
06/04/2014CN103843065A Improving sram cell writability
06/04/2014CN103838701A Data processing apparatus and method in PLC system
06/03/2014USRE44926 Operational mode control in serial-connected memory based on identifier
06/03/2014US8745464 Rank-specific cyclic redundancy check
06/03/2014US8743652 Semiconductor device having CAL latency function
06/03/2014US8743651 Clocked memory with word line activation during a first portion of the clock cycle
06/03/2014US8743650 Block repair scheme
06/03/2014US8743632 Nonvolatile memory device, operating method thereof, and data storage device having the same
06/03/2014US8742791 Method and apparatus for preamble detection for a control signal
05/2014
05/29/2014US20140146631 Vccmin for a dual port synchronous random access memory (dpsram) cell utilized as a single port synchronous random access memory (spsram) cell
05/27/2014US8737162 Clock-forwarding low-power signaling system
05/27/2014US8737161 Write-leveling system and method
05/27/2014US8737160 Semiconductor device
05/27/2014US8737159 Semiconductor memory device and method for driving the same
05/27/2014US8737158 Semiconductor device and method of controlling the same
05/27/2014US8737157 Memory device word line drivers and methods
05/27/2014US8737156 Mapping between two buses using serial addressing bits
05/27/2014US8737153 Memory device, method of operating the same, and apparatus including the same
05/22/2014US20140140162 Memory cell array with reserved sector for storing configuration information
05/22/2014US20140140145 Semiconductor device
05/20/2014US8730759 Devices and system providing reduced quantity of interconnections
05/20/2014US8730758 Adjustment of write timing in a memory device
05/20/2014US8730757 Memory system
05/20/2014US8730756 Dual clock edge triggered memory
05/20/2014US8730755 Single transistor driver for address lines in a phase change memory and switch (PCMS) array
05/20/2014US8730754 Memory apparatus and system with shared wordline decoder
05/20/2014US8730744 Semiconductor memory with redundant word lines, system, and method of manufacturing semiconductor memory
05/15/2014US20140133260 Reducing Signal Skew in Memory and Other Devices
05/15/2014US20140133259 Memory system components that support error detection and correction
05/15/2014US20140133246 Configurable embedded memory system
05/15/2014US20140133217 Concurrent use of sram cells with both nmos and pmos pass gates in a memory system
05/15/2014DE10049104B4 Hochgeschwindigkeits-Adressfolgesteuerungsgerät High-address sequence control device
05/14/2014CN103797539A 用于多端口sram的自适应读取字线电压升高设备和方法 Adaptive read word line voltage for multi-port sram rise apparatus and method
05/14/2014CN103797538A 用于存储器单元上的选择性字线升压的设备 Selective memory cells on the word line boosting device for
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