Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
03/2007
03/27/2007US7196959 Implementation of a multivibrator protected against current or voltage spikes
03/27/2007US7196957 Magnetic memory structure using heater lines to assist in writing operations
03/27/2007US7196956 Semiconductor memory device changing refresh interval depending on temperature
03/27/2007US7196954 Sensing current recycling method during self-refresh
03/27/2007US7196953 Semiconductor device using high-speed sense amplifier
03/27/2007US7196952 Column/sector redundancy CAM fast programming scheme using regular memory core array in multi-plane flash memory device
03/27/2007US7196951 Semiconductor memory
03/27/2007US7196950 Non-volatile semiconductor storage device performing ROM read operation upon power-on
03/27/2007US7196949 Semiconductor memory device with reduced skew on data line
03/27/2007US7196948 Method and apparatus for data capture on a bi-directional bus
03/27/2007US7196947 Random access memory having voltage provided out of boosted supply voltage
03/27/2007US7196946 Compensating for coupling in non-volatile storage
03/27/2007US7196944 Voltage detection circuit control device, memory control device with the same, and memory card with the same
03/27/2007US7196943 Memory device
03/27/2007US7196942 Configuration memory structure
03/27/2007US7196941 Semiconductor memory device and method for writing and reading data
03/27/2007US7196940 Method and apparatus for a multiplexed address line driver
03/27/2007US7196932 Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells
03/27/2007US7196931 Non-volatile memory and method with reduced source line bias errors
03/27/2007US7196927 Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory
03/27/2007US7196922 Programmable priority encoder
03/27/2007US7196572 Integrated circuit for stabilizing a voltage
03/27/2007US7196554 Integrated clock supply chip for a memory module, memory module comprising the integrated clock supply chip, and method for operating the memory module under test conditions
03/27/2007US7196424 Semiconductor device
03/22/2007WO2007033357A2 Semiconductor memory with reset function
03/22/2007US20070067580 Memory Access Interface for a Micro-Controller System with Address/Data Multiplexing Bus
03/22/2007US20070064512 Flash memory device and associated recharge method
03/22/2007US20070064511 Semiconductor Device
03/22/2007US20070064506 Small signal threshold and proportional gain distributed digital communications
03/22/2007US20070064505 Test mode method and apparatus for internal memory timing signals
03/22/2007US20070064504 Dual reference input receiver of semiconductor device and method of receiving input data signal
03/22/2007US20070064503 Internal Voltage Generation Control Circuit and Internal Voltage Generation Circuit Using the Same
03/22/2007US20070064502 Digital-to-analog conversion device
03/22/2007US20070064501 Wavelength-maintaining optical signal regenerator
03/22/2007US20070064500 Integrated circuit with dynamic memory allocation
03/22/2007US20070064499 Semiconductor memory device and method for writing data into the semiconductor memory device
03/22/2007US20070064498 Flash memory devices including multiple dummy cell array regions
03/22/2007US20070064485 Page buffer flash memory device and programming method using the same
03/22/2007US20070064462 Memory system and data transmission method
03/22/2007US20070063730 Variable impedence output buffer
03/22/2007DE19860799B4 Ferroelektrische Speichervorrichtung The ferroelectric memory device
03/22/2007DE102006040494A1 Halbleiterspeichersystem, Halbleiterspeicherchip und Verfahren zum Maskieren von Schreibdaten in einem Halbleiterspeicherchip A semiconductor memory system, the semiconductor memory chip and method of masking of write data in a semiconductor memory chip
03/22/2007DE102006036969A1 Elektronischer Schaltkreis, Wrapper-Schaltkreis, Speichersystem und Koppelverfahren Electronic circuit wrapper circuit storage system and the coupling method
03/22/2007DE102006035870A1 Halbleiterspeicher mit gemeinsam genutzter Schnittstelle Semiconductor memory with shared interface
03/22/2007DE102006034271A1 Spannungsstörimpulsdetektionsschaltung, zugehörige integrierte Schaltung und Steuerverfahren Spannungsstörimpulsdetektionsschaltung, associated integrated circuit and control method
03/21/2007CN2882174Y Multifunction multi-media loudspeaker
03/21/2007CN2881886Y MP3 weared on ear
03/21/2007CN2881881Y MP3 with time display
03/21/2007CN1934651A Memory device having strobe terminals with multiple functions
03/21/2007CN1933025A Programming method of non-volatile memory device having multi-plane structure
03/21/2007CN1933017A 半导体器件 Semiconductor devices
03/21/2007CN1933016A Semiconductor storage device
03/21/2007CN1933015A 半导体集成电路器件 The semiconductor integrated circuit device
03/21/2007CN1933014A Semiconductor storage device, electronic apparatus, and mode setting method
03/21/2007CN1933013A Electrostatic protecting device adapted to programmable elements
03/21/2007CN1933012A Non-volatile storage device
03/21/2007CN1933009A Structure for storing information of corresponding video frequency information object and method thereof
03/21/2007CN1932794A 电子阅读装置 Electronic reading device
03/21/2007CN1306597C Method for operating storage cells and components
03/20/2007US7194056 Determining phase relationships using digital phase values
03/20/2007US7194053 System and method for matching data and clock signal delays to improve setup and hold times
03/20/2007US7194052 Data capture circuit with self-test capability
03/20/2007US7193929 Semiconductor integrated circuit
03/20/2007US7193927 Memory device and method having banks of different sizes
03/20/2007US7193926 Memory device for reducing leakage current
03/20/2007US7193925 Low power semiconductor memory device
03/20/2007US7193924 Dual-port static random access memory having improved cell stability and write margin
03/20/2007US7193921 Cascade wake-up circuit preventing power noise in memory device
03/20/2007US7193919 Selective bank refresh
03/20/2007US7193918 Process for refreshing a dynamic random access memory and corresponding device
03/20/2007US7193917 Semiconductor storage device, test method therefor, and test circuit therefor
03/20/2007US7193916 Apparatus and method for determining erasability of data
03/20/2007US7193915 Semiconductor memory device
03/20/2007US7193914 Open digit line array architecture for a memory array
03/20/2007US7193913 Sense amplifier circuit and read/write method for semiconductor memory device
03/20/2007US7193912 Semiconductor integrated circuit device
03/20/2007US7193911 Page buffer for preventing program fail in check board program of non-volatile memory device
03/20/2007US7193910 Adjustable timing circuit of an integrated circuit
03/20/2007US7193909 Signal processing circuits and methods, and memory systems
03/20/2007US7193908 Semiconductor memory
03/20/2007US7193906 Voltage regulating circuit and method of regulating voltage
03/20/2007US7193905 RRAM flipflop rcell memory generator
03/20/2007US7193904 Random access memory with stability enhancement and early read elimination
03/20/2007US7193903 Method of controlling an integrated circuit capable of simultaneously performing a data read operation and a data write operation
03/20/2007US7193891 Spin based sensor device
03/20/2007US7193887 SRAM circuitry
03/20/2007US7193874 Content addressable memory device
03/20/2007US7193447 Differential sense amplifier latch for high common mode input
03/20/2007US7193437 Architecture for a connection block in reconfigurable gate arrays
03/20/2007US7193406 Data transmitting and receiving apparatus
03/20/2007US7193287 Magnetic memory device, a method for manufacturing a magnetic memory device, and an integrated circuit device including such magnetic memory device
03/15/2007US20070061880 Computer including at least one connector for a replaceable storage medium, and method for starting and operating a computer via a replaceable storage medium
03/15/2007US20070061537 Processor system using synchronous dynamic memory
03/15/2007US20070061536 Reconstruction of signal timing in integrated circuits
03/15/2007US20070058471 Methods and apparatus of stacking DRAMs
03/15/2007US20070058470 Serial presence detect functionality on memory component
03/15/2007US20070058469 Memory device and method having data path with multiple prefetch I/O configurations
03/15/2007US20070058468 Shielded bitline architecture for dynamic random access memory (DRAM) arrays
03/15/2007US20070058467 Semiconductor device, electro-optical device, and electronic instrument
03/15/2007US20070058462 Memory address repair without enable fuses