| Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002) |
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| 05/27/1993 | WO1993010617A1 Stand-alone device to transfer computer files using a communication line shared by a facsimile machine |
| 05/27/1993 | WO1993010499A1 Device for transmission of data |
| 05/27/1993 | DE4138033A1 Data transmission between two units coupled to common memory - using logic control unit built into one unit to generate enable signals controlling access |
| 05/27/1993 | CA2123397A1 Stand-alone device to transfer computer files using a communication line shared by a facsimile machine |
| 05/26/1993 | EP0543652A1 Memory accessing device |
| 05/26/1993 | EP0543566A2 Touch screen |
| 05/26/1993 | EP0543359A1 Bus competitive control apparatus |
| 05/26/1993 | EP0248906B1 Multi-port memory system |
| 05/26/1993 | CN1072522A Microprocessor bus inferface protocol analyzer |
| 05/26/1993 | CN1072516A Data communication interface processor for power line computer network |
| 05/25/1993 | US5214783 Device for controlling the enqueuing and dequeuing operations of messages in a memory |
| 05/25/1993 | US5214775 Hierarchy structured memory system contained in a multiprocessor system |
| 05/25/1993 | US5214774 Segmented memory transfer and message priority on synchronous/asynchronous data bus |
| 05/25/1993 | US5214772 System for automatically monitoring copiers from a remote location |
| 05/25/1993 | US5214771 System for loading same type adaptors with latest version control codes stored on adaptor memory by selecting the identified chip during initialization |
| 05/25/1993 | US5214769 Multiprocessor control system |
| 05/25/1993 | US5214767 Full address and odd boundary direct memory access controller which determines address size by counting the input address bytes |
| 05/25/1993 | US5214761 Real-time adjustable-transform device driver for physical devices |
| 05/25/1993 | US5214760 Adaptable multiple port data buffer |
| 05/25/1993 | US5214747 Segmented neural network with daisy chain control |
| 05/25/1993 | US5214423 Random number generation using volatile RAM |
| 05/25/1993 | US5214330 Bi-directional signal buffering circuit |
| 05/25/1993 | CA1318413C2 Method for memory addressing and control with reversal of higher and lower address |
| 05/25/1993 | CA1318408C Method of controlling in a quasi-parallel mode a plurality of peripheral units from a single control unit and a system for implementing this method |
| 05/23/1993 | CA2083022A1 Application specific integrated circuit for shared memory controller |
| 05/19/1993 | EP0542417A1 Method and direct memory access controller for asynchronously reading/writing data from/to a memory with improved throughput |
| 05/19/1993 | EP0542087A2 Method and apparatus for efficient serialized transmission of handshake signal on a digital bus |
| 05/19/1993 | CN1020815C Bus master interface circuit with transparent preemption of data transfer operation |
| 05/19/1993 | CN1020814C Method for unblocking multibus multiprocessor system |
| 05/19/1993 | CN1020813C Programmable interrupt controller |
| 05/19/1993 | CN1020812C Apparatus and method for guaranteeing strobe seperation timing |
| 05/19/1993 | CN1020811C Method and apparatus for dynamically managing input/output (i/o) connectivity |
| 05/19/1993 | CN1020810C Dual microprocessor control system |
| 05/18/1993 | US5212801 Apparatus for responding to completion of each transition of a driver output signal for damping noise by increasing driver output impedance |
| 05/18/1993 | US5212796 System with modules using priority numbers related to interrupt vectors for bit-serial-arbitration on independent arbitration bus while CPU executing instructions |
| 05/18/1993 | US5212795 Programmable DMA controller |
| 05/18/1993 | US5212781 Secondary cache control for a computer system |
| 05/18/1993 | US5212776 Computer system comprising a main bus and an additional communication means directly connected between processor and main memory |
| 05/18/1993 | US5212772 System for storing data in backup tape device |
| 05/18/1993 | CA1318040C Electronic mail follow-up system |
| 05/18/1993 | CA1318037C Data processing system bus architecture |
| 05/18/1993 | CA1318036C Method for confirming selected activities by recipients of electronic mail |
| 05/13/1993 | WO1993009505A1 Data transmission line interface device |
| 05/13/1993 | WO1993009503A1 Sampling buffer for field programmable interconnect device |
| 05/12/1993 | EP0541288A2 Circuit module redundacy architecture |
| 05/12/1993 | EP0540831A1 Coupling unit for coupling a computer to intelligent and dumb terminals |
| 05/12/1993 | EP0509068A4 Dynamic association of rf radio data communication system in a pre-existing computer controlled network |
| 05/12/1993 | EP0490988A4 Enhanced vmebus protocol utilizing pseudosynchronous handshaking and block mode data transfer |
| 05/12/1993 | EP0393173B1 Data bus enable verification logic |
| 05/12/1993 | EP0364557B1 A method and apparatus for stabilized data transmission |
| 05/12/1993 | EP0209565B1 Printer-tape data link processor |
| 05/11/1993 | US5210862 Bus monitor with selective capture of independently occuring events from multiple sources |
| 05/11/1993 | US5210855 System for computer peripheral bus for allowing hot extraction on insertion without disrupting adjacent devices |
| 05/11/1993 | US5210852 Memory control system for controlling a first and second processing means to individually access a plurality of memory blocks |
| 05/11/1993 | US5210846 One-wire bus architecture |
| 05/11/1993 | US5210830 Dynamic reconfiguration of UART polling loop with a jump table |
| 05/11/1993 | US5210827 Nest level judging device for judging the starting and the end addresses |
| 05/11/1993 | US5210747 Communications controller for use with a computer and a plurality of isdn terminals |
| 05/11/1993 | US5210745 Frame restructuring interface for digital bit streams multiplexed by time-division multiplexing digital tributaries with different bit rates |
| 05/11/1993 | US5210682 Radial type of parallel system bus structure having pairs of conductor lines with impedance matching elements |
| 05/11/1993 | US5210535 O S I data communication for dealing with abstract syntaxes which are and are not preliminarily negotiated |
| 05/11/1993 | US5210531 Monitoring and control system with binary addressing |
| 05/11/1993 | US5210529 Bit finder circuit |
| 05/11/1993 | CA1317682C System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration |
| 05/11/1993 | CA1317676C Address detection circuit using a memory |
| 05/11/1993 | CA1317651C Protocol for network having a plurality of intelligent cells |
| 05/05/1993 | EP0540450A1 ECC function with self-contained high performance partial write or read/modify/write and parity look-ahead interface scheme |
| 05/05/1993 | EP0540449A1 High speed bus transceiver with fault tolerant design for hot pluggable applications |
| 05/05/1993 | EP0540427A1 Interface circuit for IC card |
| 05/05/1993 | EP0540363A1 Data processing system |
| 05/05/1993 | EP0540206A2 Information handling apparatus allowing direct memory access |
| 05/05/1993 | EP0540205A1 Information handling system including direct accessing of memory |
| 05/05/1993 | EP0540187A1 Apparatus for electrically switching between peripheral devices |
| 05/05/1993 | EP0540166A2 Secure object equivalency determination |
| 05/05/1993 | EP0540151A2 Method of operating a computer in a network |
| 05/05/1993 | EP0540001A1 Bus contention resolution method for extended distances |
| 05/05/1993 | EP0539840A2 Method and circuit for the transmission of data blocks on a bus system |
| 05/05/1993 | EP0539796A2 Method for data collision detection in a multi-processor communication system |
| 05/05/1993 | EP0539783A1 Circuit for controlling data transfer from SCSI disk drive to VME bus |
| 05/05/1993 | EP0539782A1 Circuit for controlling data transfer from VME bus to SCSI disk drive |
| 05/05/1993 | EP0539494A1 High-speed, high-capacity, fault-tolerant, error-correcting storage system for binary computers |
| 05/05/1993 | CN1071773A Multi-bus digital signal processing system on the bus of personal computer system |
| 05/05/1993 | CN1071772A Method for setting up system configuration in data processing system, data processing system, and expasion unit for data processing system |
| 05/05/1993 | CN1020512C File extension by clients in distributed data processing system |
| 05/04/1993 | US5208915 Apparatus for the microprogram control of information transfer and a method for operating the same |
| 05/04/1993 | US5208912 Joint information processing system comprising a plurality of terminal apparatuses guaranteeing identicalness of data processing results |
| 05/04/1993 | US5208562 Bus terminator circuit having RC elements |
| 05/04/1993 | CA1317380C Universal connector device |
| 05/01/1993 | CA2074879A1 Memory system and unique memory chip allowing island interlace |
| 04/30/1993 | CA2080882A1 Method and circuit arrangement for transmitting data blocks through a bus system |
| 04/29/1993 | WO1993008654A1 Wireless transmitting and receiving device with selectable channel settings |
| 04/29/1993 | WO1993008532A2 Basic input/output system (bios) program storage on a motherboard for a variety of computer cpu types |
| 04/29/1993 | WO1993008524A1 System for dividing processing tasks into signal processor and decision-making microprocessor interfacing |
| 04/29/1993 | WO1993008029A1 Apparatus and method for processing information, and additional control device used therein |
| 04/29/1993 | WO1993008028A1 Apparatus and method for processing information, and additional control device used therein |
| 04/29/1993 | WO1993008027A1 Additional control device, and apparatus and method for processing information thereby |
| 04/29/1993 | DE4135471A1 Connector cable to link PC to sewing machine - has logic level converter in 25 pin end connector, and TTL inputs on DIN plug at other cable end, to interface sewing machine |
| 04/28/1993 | EP0539313A2 Method and apparatus for simulating I/O devices |
| 04/28/1993 | EP0539130A2 Communication within a data processing system |
| 04/28/1993 | EP0539077A1 Information handling system with CPU bus allocation control |