| Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002) |
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| 02/25/1993 | DE4128193A1 Serial output of synchronous data via asynchronous interface - outputting bit sequence via control line, switched w.r.t. required Baud rate |
| 02/24/1993 | EP0528773A1 A system for performing dynamically the configuration of expansion boards on personal computers having a standard bus |
| 02/24/1993 | EP0528730A1 Method for emitting and receiving personalized programs |
| 02/24/1993 | EP0528703A1 Structure of a set of communicating programmable logic controllers |
| 02/24/1993 | EP0528538A2 Mirrored memory multi processor system |
| 02/24/1993 | EP0528396A2 Method of controlling an industrial process |
| 02/24/1993 | EP0528273A2 Buffer memory and method of managing the same |
| 02/24/1993 | EP0528139A1 Programmable interrupt priority encoder method and apparatus |
| 02/24/1993 | EP0528060A1 Procedure for input/output operations in computer systems |
| 02/24/1993 | EP0512993A4 Bus locking fifo multi-processor communication system |
| 02/24/1993 | EP0436641A4 Computer three-way transfer operation |
| 02/24/1993 | EP0371034A4 Method and apparatus for data buffer management |
| 02/24/1993 | CN1069355A Electronic information exchange servo device |
| 02/23/1993 | CA2073540A1 Multiprocessor system, memory managing system therefor, and graphics display system using the multiprocessor system |
| 02/20/1993 | CA2070348A1 Multifunctional document processing system |
| 02/18/1993 | WO1993003442A1 Multiboard multiprocessor connector system |
| 02/18/1993 | WO1993003440A1 High-speed bus system and process for operating same |
| 02/18/1993 | WO1993003439A1 Apparatus and method for frame switching |
| 02/18/1993 | WO1993003438A1 Intelligent hardware for automatically reading and writing multiple sectors of data between a computer bus and a disk drive |
| 02/18/1993 | DE4226086A1 Microcomputer system - has remote terminal processor operations handled in real time without using CPU to control signal transmission |
| 02/18/1993 | DE4126850A1 Circuit for matching data bus controller to symmetrical bus line - has filters for attenuating HF components, and evaluation delay which is set longer than filter delay |
| 02/17/1993 | EP0527590A2 Distributed application execution |
| 02/17/1993 | EP0527557A1 Signal arbitration circuits and methods using superconductive elements |
| 02/17/1993 | EP0527260A1 Interface unit for supporting the communication between processor systems |
| 02/17/1993 | EP0263886B1 Interrupt control method in a multiprocessor system |
| 02/16/1993 | US5187791 Microprocessor with improved interrupt response with data saving dependent upon processor status using status flag |
| 02/16/1993 | US5187787 Apparatus and method for providing decoupling of data exchange details for providing high performance communication between software processes |
| 02/16/1993 | US5187783 Controller for direct memory access |
| 02/16/1993 | US5187781 Shared hardware interrupt circuit for personal computers |
| 02/16/1993 | US5187779 Memory controller with synchronous processor bus and asynchronous i/o bus interfaces |
| 02/13/1993 | CA2075449A1 I/o controller apparatus and method for transferring data between a host processor and multiple i/o units |
| 02/13/1993 | CA2072720A1 Programmable interrupt priority encoder method and apparatus |
| 02/11/1993 | DE4219172A1 Data transfer circuit between data processing and transmission systems - handles data in two separate data memories with higher order address provided by common unit and lower order by separate units |
| 02/11/1993 | DE4125954A1 Parallel input-output interface for personal computer - has slot connection with parallel input-output registers for coupling to external systems |
| 02/10/1993 | EP0526930A1 A processor buffered interface for multiprocessor systems |
| 02/10/1993 | EP0526688A2 Coupling device for transmitting data and/or control signals between a radiotelephone station and a computer |
| 02/10/1993 | EP0526580A1 Multichannel backplane bus system architecture |
| 02/10/1993 | EP0346388B1 High speed raster image processor |
| 02/09/1993 | US5185877 Protocol for transfer of DMA data |
| 02/09/1993 | US5185876 Buffering system for dynamically providing data to multiple storage elements |
| 02/09/1993 | US5185865 System for simulating block transfer with slave module incapable of block transfer by locking bus for multiple individual transfers |
| 02/09/1993 | US5185864 Interrupt handling for a computing system with logical devices and interrupt reset |
| 02/09/1993 | US5185862 Apparatus for constructing data frames for transmission over a data link |
| 02/09/1993 | US5185860 Automatic discovery of network elements |
| 02/09/1993 | US5185706 Programmable gate array with logic cells having configurable output enable |
| 02/09/1993 | US5185694 Data processing system utilizes block move instruction for burst transferring blocks of data entries where width of data blocks varies |
| 02/09/1993 | US5185692 Computer security device having connector with spring loaded contact members |
| 02/04/1993 | WO1993002423A1 Communication apparatus and method for transferring image data from a source to one or more receivers |
| 02/04/1993 | WO1993002421A1 Method and device for forming a dynamic priority |
| 02/04/1993 | WO1993002420A1 Computer workstation expansion chassis |
| 02/04/1993 | DE4209889A1 Control device for direct access to operating medium - increases priority sequence for async. operating medium and reduces DMA operating condition for sync. operating medium |
| 02/04/1993 | DE4125219A1 Hochgeschwindigkeits-bussystem und verfahren zum betreiben desselben High-speed bus system and process thereof to operate |
| 02/03/1993 | EP0526183A2 Computer-printer data transfer method |
| 02/03/1993 | EP0525985A2 High speed data link interface |
| 02/03/1993 | EP0525963A2 Generation of a clock frequency in a smart card interface |
| 02/03/1993 | EP0525860A2 High performance I/O processor |
| 02/03/1993 | EP0525845A1 Multiplexing system for subchannels with different priority levels |
| 02/03/1993 | EP0525792A2 Image editing system for transmission network supervision |
| 02/03/1993 | EP0525749A1 Memory control device |
| 02/03/1993 | EP0525736A1 Data storing system for a communication control circuit |
| 02/03/1993 | EP0525667A1 Remote control signal processing circuit for a microcomputer |
| 02/03/1993 | EP0525233A1 Method and apparatus for data transfer between system bus and memory by direct memory access transfer |
| 02/03/1993 | EP0525232A1 Apparatus to realise similar peripheral connecting devices as access devices for different peripheral devices to a common bus |
| 02/03/1993 | EP0525221A1 Quasi-synchronous information transfer and phase alignment means for enabling same |
| 02/03/1993 | EP0525068A1 Integrated circuit i/o using a high preformance bus interface |
| 02/03/1993 | EP0524945A1 Data storage subsystem |
| 02/03/1993 | EP0524940A1 Channel selection arbitration |
| 02/02/1993 | US5184282 IC card adapter |
| 02/02/1993 | US5183404 Systems for connection of physical/electrical media connectors to computer communications cards |
| 02/02/1993 | CA1313422C2 Cache memory control system |
| 02/02/1993 | CA1313414C Data processing system having a shared bus and a priority determination circuit therefor |
| 01/27/1993 | EP0524810A2 Recording information sent by host computer over a SCSI-bus |
| 01/27/1993 | EP0524773A1 Multiple command set support for rendering components |
| 01/27/1993 | EP0524684A2 A universal buffered interface for coupling multiple processors, memory units, and I/O interfaces to a common high-speed bus |
| 01/27/1993 | EP0524683A1 Scientific visualization system |
| 01/27/1993 | EP0524682A1 A centralized backplane bus arbiter for multiprocessor systems |
| 01/27/1993 | EP0524530A1 DMA controller |
| 01/27/1993 | EP0524203A1 Method and apparatus for an enhanced computer system interface |
| 01/27/1993 | EP0524199A1 Telecommunication interface apparatus and method |
| 01/26/1993 | US5182811 Exception, interrupt, and trap handling apparatus which fetches addressing and context data using a single instruction following an interrupt |
| 01/26/1993 | US5182808 Multiprocessor systems having distributed shared resources and deadlock prevention |
| 01/26/1993 | US5182801 Apparatus and method for providing fast data transfer between multiple devices through dynamic reconfiguration of the memory space of the devices |
| 01/26/1993 | US5182800 Direct memory access controller with adaptive pipelining and bus control features |
| 01/26/1993 | US5182746 Transceiver interface |
| 01/26/1993 | US5182554 Third party evavesdropping for bus control |
| 01/26/1993 | CA1313263C Apparatus and method for tracking and identifying printed circuit assemblies |
| 01/23/1993 | CA2068580A1 Scientific visualization system |
| 01/21/1993 | WO1993001553A1 Microprocessor architecture capable of supporting multiple heterogeneous processors |
| 01/21/1993 | WO1993001552A1 Asynchronous modular bus architecture with burst capability |
| 01/21/1993 | WO1993001326A1 A composition of matter for coating a press roll |
| 01/21/1993 | DE4223454A1 Digital signal processor with direct memory access controller - performs different transfers of data according to relationship of input-output period to task processing time |
| 01/21/1993 | CA2074008A1 Quasi-synchronous information transfer and phase alignment means for enabling same |
| 01/20/1993 | EP0524123A2 Compensation for mismatched transport protocols in a data communications network |
| 01/20/1993 | EP0524089A1 Software structure for a data processing system, especially for a telecommunications system |
| 01/20/1993 | EP0524077A1 Software structure for an information processing system |
| 01/20/1993 | EP0524071A1 Operating system for a universal device coupling a computer bus to a specific network |
| 01/20/1993 | EP0524070A1 Universal coupling device between a computer bus and a controller of a group of peripherals |
| 01/20/1993 | EP0523881A2 Data processing system |
| 01/20/1993 | EP0523878A1 Deterministic method for allocation of a shared resource |
| 01/20/1993 | EP0523764A2 Computer system having direct bus attachment between processor and dynamic main memory, and having in-processor DMA control with respect to a plurality of data exchange means also connected to said bus, and central processor for use in such computer system |