| Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002) |
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| 09/29/1993 | EP0562746A1 Apparatus and method for transferring data between buses of different widths |
| 09/29/1993 | EP0562728A2 Computer display of video |
| 09/29/1993 | EP0562704A1 Microprocessor controlled apparatus |
| 09/29/1993 | EP0562222A1 Access control arrangement |
| 09/29/1993 | EP0562151A1 Integrated microprocessor |
| 09/29/1993 | EP0562022A1 Method and apparatus for multiprocessor digital communication |
| 09/29/1993 | EP0556314A4 Method and apparatus for providing down-loaded instructions for execution by a peripheral controller |
| 09/29/1993 | EP0346401B1 Commander node method and apparatus for assuring adequate access to system ressources in a multiprocessor computer system |
| 09/28/1993 | US5249297 Methods and apparatus for carrying out transactions in a computer system |
| 09/28/1993 | US5249271 Buffer memory data flow controller |
| 09/28/1993 | US5249270 Development system protocol |
| 09/28/1993 | US5248908 3-state bidirectional buffer and portable semiconductor storage device incorporating the same |
| 09/28/1993 | US5248905 High speed, master/slave latch transceiver having a directly-driven slave stage |
| 09/28/1993 | CA2092245A1 Access control arrangement |
| 09/28/1993 | CA1322612C Interface between a system control unit and a service processing unit of a digital computer |
| 09/28/1993 | CA1322611C Memory control unit |
| 09/28/1993 | CA1322608C System bus having multi-plexed command/id and data |
| 09/28/1993 | CA1322605C Parity checking apparatus |
| 09/23/1993 | DE4308508A1 Bidirectional signal transmission system for computer system - has logic units with ECL transmitter stages providing impedance values related to characteristics line impedance for optimum transmission |
| 09/23/1993 | DE4207573A1 Parallele schnittstelle zum verbinden von datenverarbeitungsgeraeten Parallel interface for connecting to computers |
| 09/22/1993 | EP0560965A1 Temporary message routing and destination selection |
| 09/21/1993 | US5247694 System and method for generating communications arrangements for routing data in a massively parallel processing system |
| 09/21/1993 | US5247685 Interrupt handling in an asymmetric multiprocessor computer system |
| 09/21/1993 | US5247683 System and method for installing software and updating configuration files |
| 09/21/1993 | US5247682 System and method for the automatic setting of a computer system's I/O configuration |
| 09/21/1993 | US5247671 Scalable schedules for serial communications controller in data processing systems |
| 09/21/1993 | US5247670 Network server |
| 09/21/1993 | US5247663 Method and apparatus for constructing continued entry fields with multiple terminals |
| 09/21/1993 | US5247661 Method and apparatus for automated document distribution in a data processing system |
| 09/21/1993 | US5247657 Serial data transmission including idle bits |
| 09/21/1993 | US5247642 Apparatus for determining cacheability of a memory address to provide zero wait state operation in a computer system |
| 09/21/1993 | US5247627 Digital signal processor with conditional branch decision unit and storage of conditional branch decision results |
| 09/21/1993 | US5247622 Id processing dedicated scsi bus interface logic circuit |
| 09/21/1993 | US5247621 System and method for processor bus use |
| 09/21/1993 | US5247619 Insertion and removal of a circuit device into a bus network |
| 09/21/1993 | US5247617 Method for supplying data to a buffered uart |
| 09/21/1993 | US5247614 Method and apparatus for distributed processing of display panel information |
| 09/21/1993 | US5247485 Memory device |
| 09/21/1993 | CA1322420C Dynamic burst control for data transfers |
| 09/16/1993 | WO1993018463A1 Method and circuitry for minimizing clock-data skew in a bus system |
| 09/16/1993 | WO1993018462A1 High speed bus system |
| 09/16/1993 | WO1993018461A1 High-performance non-volatile ram protected write cache accelerator system |
| 09/16/1993 | WO1993018453A1 Use of a language having a similar representation for programmes and data in distributed data processing |
| 09/16/1993 | WO1993018451A1 Elimination of the critical path in memory control unit and input/output control unit operations |
| 09/16/1993 | WO1993018449A1 Parallel interface for connecting data processing machines |
| 09/16/1993 | WO1993018446A1 Accelerated token ring network |
| 09/16/1993 | CA2131627A1 High-performance non-volatile ram protected write cache accelerator system |
| 09/15/1993 | EP0560689A1 Use of a programming language, which has types associated with data, in a network management system |
| 09/15/1993 | EP0560343A1 Input-output control system and input-output control method in the system |
| 09/15/1993 | EP0560020A2 Digital signal processing function appearing as hardware FIFO |
| 09/15/1993 | EP0559824A1 Binary data communication system |
| 09/15/1993 | EP0559821A1 Low cost communication terminal |
| 09/15/1993 | EP0559736A1 Medicament dispensing device. |
| 09/15/1993 | EP0398881B1 Memory controller as for a video signal processor |
| 09/15/1993 | EP0303661B1 Central processor unit for digital data processing system including write buffer management mechanism |
| 09/14/1993 | US5245703 Data processing system with multiple communication buses and protocols |
| 09/14/1993 | US5245575 Register circuit for copying contents of one register into another register |
| 09/14/1993 | US5245532 Electronic mail follow-up system |
| 09/14/1993 | US5245322 Bus architecture for a multimedia system |
| 09/14/1993 | US5245320 Multiport game card with configurable address |
| 09/11/1993 | CA2062583A1 Serial data switchboard |
| 09/09/1993 | DE4305851A1 Data transfer system between memory and central processing unit - uses direct memory access transfer control having bus information control stage to provide time priority access control of operations |
| 09/09/1993 | DE4207129A1 Large display facility for computer graphics systems - uses multiple standard monitors receiving input from circuit converting output of graphics software |
| 09/08/1993 | EP0559454A1 On-line module replacement in a multiple module data processing system |
| 09/08/1993 | EP0559409A1 A method and apparatus for performing a bus arbitration protocol in a data processing system |
| 09/08/1993 | EP0559408A1 A method and apparatus for performing bus arbitration using an arbiter in a data processing system |
| 09/08/1993 | EP0559339A2 Linking elements of a data processing complex |
| 09/08/1993 | EP0559214A1 Event driven commnication network |
| 09/08/1993 | EP0559205A1 Data processing system |
| 09/08/1993 | EP0558935A2 Communications adapter between two way alternate and two way simultaneous communication links |
| 09/08/1993 | EP0558926A1 Efficient channel and control unit for host computer |
| 09/08/1993 | EP0558770A1 A hot pluggable electrical circuit |
| 09/08/1993 | CN1022078C Microcomputer distributed networking method and computer network card |
| 09/07/1993 | US5243703 Apparatus for synchronously generating clock signals in a data processing system |
| 09/07/1993 | US5243702 Minimum contention processor and system bus system |
| 09/07/1993 | US5243700 Port expander architecture for mapping a first set of addresses to external memory and mapping a second set of addresses to an I/O port |
| 09/07/1993 | US5243623 Switchable multi-mode transceiver interface device |
| 09/07/1993 | US5243543 Remote LAN segment traffic monitor |
| 09/07/1993 | CA2091076A1 Method for storing programs |
| 09/07/1993 | CA2089940A1 On-line module replacement in a multiple data processing system |
| 09/07/1993 | CA1322057C Method and apparatus for configuration of computer system and circuit boards |
| 09/07/1993 | CA1322034C Bidirectional control signalling bus interface apparatus for transmitting signals between two bus systems |
| 09/03/1993 | CA2086853A1 Communications adapter between two way alternate and two way simultaneous communication links |
| 09/02/1993 | WO1993017389A1 Externally updatable rom (eurom) |
| 09/01/1993 | EP0558433A2 Independent computer storage addressing in input/output transfers |
| 09/01/1993 | EP0558234A1 Ethernet media access controller with external address detection interface |
| 09/01/1993 | EP0557959A1 Modulation/demodulation apparatus and information processing apparatus |
| 09/01/1993 | EP0557699A1 Method and apparatus for verifying interruptsignals in microprocessor-systems |
| 09/01/1993 | EP0557582A1 Clock re-generating circuit for system controller |
| 09/01/1993 | EP0312575B1 High performance low pin count bus interface |
| 09/01/1993 | EP0312573B1 Backplane bus |
| 08/31/1993 | US5241682 Border node having routing and functional capability in a first network and only local address capability in a second network |
| 08/31/1993 | US5241681 Computer system having an internal cach microprocessor slowdown circuit providing an external address signal |
| 08/31/1993 | US5241680 Low-power, standby mode computer |
| 08/31/1993 | US5241666 For use in a data processing system |
| 08/31/1993 | US5241661 DMA access arbitration device in which CPU can arbitrate on behalf of attachment having no arbiter |
| 08/31/1993 | US5241632 Programmable priority arbiter |
| 08/31/1993 | US5241631 Personal computer having a local bus interface to a video circuit |
| 08/31/1993 | US5241630 Device controller with a separate command path between a host and the device and a separate data path including a first in, first out memory between the host and the device |
| 08/31/1993 | US5241629 Method and apparatus for a high performance round robin distributed bus priority network |