Patents
Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002)
01/1994
01/20/1994CA2139744A1 Trusted path subsystems for workstations
01/20/1994CA2138654A1 Multiport game card with configurable address
01/19/1994EP0579529A1 Device for the connection of a terminal to a local network having at least one ring
01/19/1994EP0579515A1 Asynchronous bus interface for minimising asynchronous bus data transfer times
01/19/1994EP0579398A1 Method of addressing devices and transferring data signals on a bus
01/19/1994EP0579397A1 Method of determining devices requesting the transfer of data signals on a bus
01/19/1994EP0579390A2 A justifier and de-justifier
01/19/1994EP0579389A1 Source synchronized metastable free bus
01/19/1994EP0579387A1 Computer interconnection assembly
01/19/1994EP0579040A2 Connection protection in a digital telecommunications system
01/19/1994EP0579029A2 Connection protection in a digital telecommunications system
01/19/1994EP0578924A1 Host communication message manager for a label printing system with data collection capabilities
01/19/1994EP0578749A1 Apparatus and method for fast i/o transfer
01/19/1994CN1081035A Global load smoothing in a real time data imaging network system
01/19/1994CN1081007A A real time data imaging network system and a method of operating same
01/18/1994US5280628 Interruption controlling system using timer circuits
01/18/1994US5280627 Remote bootstrapping a node over communication link by initially requesting remote storage access program which emulates local disk to load other programs
01/18/1994US5280623 Versatile peripheral bus
01/18/1994US5280621 Personal computer having dedicated processors for peripheral devices interconnected to the CPU by way of a system control processor
01/18/1994US5280610 Methods and apparatus for implementing data bases to provide object-oriented invocation of applications
01/18/1994US5280598 Cache memory and bus width control circuit for selectively coupling peripheral devices
01/18/1994US5280597 Pipeline processor with self timed data transfer
01/18/1994US5280596 Write-acknowledge circuit including a write detector and a bistable element for four-phase handshake signalling
01/18/1994US5280594 Architecture for high speed contiguous sequential access memories
01/18/1994US5280591 Centralized backplane bus arbiter for multiprocessor systems
01/18/1994US5280590 Logic support chip for AT-type computer with improved bus architecture
01/18/1994US5280589 Memory access control system for use with a relatively small size data processing system
01/18/1994US5280588 Computer system
01/18/1994US5280587 Computer system in which a bus controller varies data transfer rate over a bus based on a value of a subset of address bits and on a stored value
01/18/1994US5280586 Expandable communication system using data concentration
01/18/1994US5280584 Two-way data transfer apparatus
01/18/1994US5280580 System service request processing in multiprocessor environment
01/18/1994US5280515 Fault processing system for processing faults of producing points
01/18/1994US5280482 Time-sharing data transfer apparatus
01/18/1994US5280480 Source routing transparent bridge
01/12/1994EP0578496A2 Job execution method in multi-CPU system
01/12/1994EP0578416A1 Computer fiber optic interface
01/12/1994EP0578386A2 Hierarchical connection method, apparatus and protocol
01/12/1994EP0578257A1 System and method for mode switching
01/12/1994EP0578139A2 Programmable disk drive array controller
01/12/1994EP0578041A2 Shortcut network layer routing for mobile hosts
01/12/1994EP0578013A1 Improved input/output control system and method
01/12/1994EP0577778A1 Transceiver interface
01/12/1994EP0393117B1 Protocol for network having a plurality of intelligent cells
01/12/1994EP0329664B1 Arbitration technique for a split transaction bus in a multprocessor computer system
01/11/1994US5278974 Method and apparatus for the dynamic adjustment of data transfer timing to equalize the bandwidths of two buses in a computer system having different bandwidths
01/11/1994US5278968 Microprocessor capable of transferring data without intermediating execution unit
01/11/1994US5278965 Direct memory access controller
01/11/1994US5278957 Data transfer circuit for interfacing two bus systems that operate asynchronously with respect to each other
01/11/1994US5278956 Data communications device
01/11/1994US5278955 Open systems mail handling capability in a multi-user environment
01/11/1994US5278836 Multichannel communication processing system
01/11/1994US5278834 Method for implementing a data communication protocol stack
01/11/1994US5278800 Memory system and unique memory chip allowing island interlace
01/11/1994US5278730 Modular notebook computer having a planar array of module bays
01/11/1994CA2100188A1 Device for branching a station to a local area network having at least one ring
01/06/1994WO1994000970A1 Modular notebook computer
01/06/1994WO1994000834A1 Improved vga controller having frame buffer memory arbitration and method therefor
01/06/1994WO1994000815A1 Virtual radio interface
01/06/1994WO1994000814A1 Virtual data source
01/06/1994WO1993021581A3 Cryptographic data security in a secured computer system
01/05/1994EP0577431A2 Method of resetting coupled modules and a system using the method
01/05/1994EP0577370A1 Image processing system
01/05/1994EP0577115A2 Programmed I/O Ethernet adapter with early interrupts for accelerating data transfer
01/05/1994EP0577110A2 Dual bus local area metwork interfacing system
01/05/1994EP0577006A1 Four-lines serial bus
01/05/1994EP0576764A1 Method and apparatus for managing the access to a resource by several users in a data processing system
01/05/1994EP0576711A1 Data processing system with several clock frequencies
01/05/1994EP0576546A1 Networked variables
01/05/1994EP0287678B1 Data transfer system having transfer discrimination circuit
01/05/1994EP0198170B1 A monitor circuit
01/05/1994DE4305017A1 Data processor and peripherals on system bus - employs multibit code key read by processor in two access operations distinguished by variation of potentials on two lines
01/05/1994DE4221410A1 Bus system for bar=code readers with address connection pins - employs numbering of pins for encoding of reader address within range of 2 to the power n different values
01/05/1994DE4220258A1 Bit-serial data processor adaptable to various data structures - makes serial data available in parallel before transmission and reconstructible as parallel data word after transmission
01/05/1994CN2152206Y Multifunction signal analyser
01/04/1994US5276900 Master connected to common bus providing synchronous, contiguous time periods having an instruction followed by data from different time period not immediately contiguous thereto
01/04/1994US5276896 Apparatus for implementing data communications between terminal devices and user programs
01/04/1994US5276887 Bus arbitration system for granting bus access to devices following two-wire bus arbitration protocol and devices following three-wire bus arbitration protocol
01/04/1994US5276886 Hardware semaphores in a multi-processor environment
01/04/1994US5276883 System and method for uniform control of local and remote applications in a data processing network
01/04/1994US5276879 Portable, resource sharing file server using co-routines
01/04/1994US5276869 System for selecting document recipients as determined by technical content of document and for electronically corroborating receipt of document
01/04/1994US5276861 Guaranteed message delivery from a data handling computer to management computer by monitoring the management computer with the data handling computer and other management computer
01/04/1994US5276859 Accelerated token ring network
01/04/1994US5276857 Data processing system with shared control signals and a state machine controlled clock
01/04/1994US5276845 Apparatus with multiple buses for permitting concurrent access to a first memory by a processor while a DMA transfer is occurring between a second memory and a communications buffer
01/04/1994US5276842 Dual port memory
01/04/1994US5276838 In a data processing memory system
01/04/1994US5276836 Data processing device with common memory connecting mechanism
01/04/1994US5276818 Bus system for information processing system and method of controlling the same
01/04/1994US5276816 Icon object interface system and method
01/04/1994US5276815 Input and output processing system for a virtual computer
01/04/1994US5276814 Method for transferring information between main store and input output bus units via a sequence of asynchronous bus and two synchronous buses
01/04/1994US5276813 Acquiring addresses in an input/output system
01/04/1994US5276808 Method for striping data
01/04/1994US5276807 Bus interface synchronization circuitry for reducing time between successive data transmission in a system using an asynchronous handshaking
01/04/1994US5276801 Data processing system for notifying a terminal user of an asynchronous event occurrence
01/04/1994US5276781 Laser printer controller flexible frame buffer architecture which allows hardware assisted memory erase
01/04/1994US5276735 Data enclave and trusted path system
01/04/1994US5276684 Communication apparatus