| Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002) |
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| 08/18/1992 | US5140679 Universal asynchronous receiver/transmitter |
| 08/18/1992 | CA1306550C Apparatus and method for determining access to a bus |
| 08/18/1992 | CA1306544C High speed relational data base processor |
| 08/12/1992 | EP0498751A1 Apparatus and method for communicating between nodes in a network |
| 08/12/1992 | EP0498595A2 Flexible single chip digital processor architecture |
| 08/12/1992 | EP0498472A2 Microprocessor for retrying data transfer |
| 08/12/1992 | EP0498454A2 Signal processing apparatus |
| 08/12/1992 | EP0498201A2 Generic high bandwidth adapter architecture |
| 08/12/1992 | EP0498065A2 Variable data stripe system and method |
| 08/12/1992 | EP0497986A1 Memory access system |
| 08/12/1992 | EP0377022A4 Computing machine with hybrid communication architecture |
| 08/12/1992 | CN1063564A Automatic device configuration for dockable portable computers |
| 08/12/1992 | CN1017839B Apparatus and method for decreasing the memory requirements for bios in a personal computer system |
| 08/12/1992 | CN1017837B Main storage memory cards having single bit set and reset functions |
| 08/11/1992 | US5138706 Password protected enhancement configuration register for addressing an increased number of adapter circuit boards with target machine emulation capabilities |
| 08/11/1992 | US5138703 Method of and apparatus for expanding system bus |
| 08/11/1992 | US5138701 Data communication control system |
| 08/11/1992 | US5138620 Communication control system |
| 08/11/1992 | US5138611 Blocking message transmission or signaling error in response to message addresses in a computer interconnect coupler for clusters of data processing devices |
| 08/11/1992 | US5138610 Method of controlling in a quasi-parallel mode a plurality of peripheral units from a single control unit and system for implementing this mode |
| 08/11/1992 | CA1306318C Computer and telephone apparatus with user friendly computer interface and enhanced integrity features |
| 08/11/1992 | CA1306311C I/o system for off-loading operating system functions |
| 08/11/1992 | CA1306310C Distributed computer system |
| 08/06/1992 | WO1992013414A1 Packet transmission system and method utilizing both a data bus and dedicated control lines |
| 08/06/1992 | WO1992013313A1 Mixed resolution, n-dimensional object space |
| 08/06/1992 | WO1992013309A1 Method and apparatus for scoped interprocess message switching |
| 08/05/1992 | EP0497628A2 Interrupt controller for a multiprocessor computer system |
| 08/05/1992 | EP0497504A2 Attachment identifier for information processing system |
| 08/05/1992 | EP0497442A2 Multi-peripheral controller |
| 08/05/1992 | EP0497441A2 Improved microprocessor synchronous timing system |
| 08/05/1992 | EP0497380A2 Microcomputer having a watchdog timer |
| 08/05/1992 | EP0497054A2 Apparatus and method for a synchronous, high speed, packet-switched bus |
| 08/05/1992 | EP0496922A1 Method and circuit layout for control of the transmission of data between one of several input/output modules and another unit of a data processing system |
| 08/05/1992 | EP0496919A1 Method to chronologically order accesses of units for data transmission and processing to a multiport area |
| 08/05/1992 | EP0496878A1 Offset-based dma mechanism |
| 08/05/1992 | CN1063391A Microcomputer structure type networking method and three-dimensional computer network card |
| 08/05/1992 | CN1063374A Mixed-resolution, n-dimensional object space method and apparatus |
| 08/04/1992 | US5136716 Session control in network for digital data processing system which supports multiple transfer protocols |
| 08/04/1992 | US5136715 Terminal apparatus for resetting by remote control |
| 08/04/1992 | US5136713 Apparatus and method for decreasing the memory requirements for bios in a personal computer system |
| 08/04/1992 | US5136709 Method for generating an operating system by a static link-editor |
| 08/04/1992 | US5136707 Reliable database administration arrangement |
| 08/04/1992 | US5136701 Processing unit containing DMA controller having concurrent operation with processor wherein addresses and data are divided into two parts |
| 08/04/1992 | US5136681 Optical powder attenuator of variable attenuation type |
| 08/04/1992 | US5136590 Kernel testing interface and method for automating diagnostics of microprocessor-based systems |
| 08/04/1992 | US5136582 Memory management system and method for network controller |
| 08/04/1992 | US5136500 Multiple shared memory arrangement wherein multiple processors individually and concurrently access any one of plural memories |
| 08/04/1992 | US5136498 Method for enacting failover of a 1:1 redundant pair of slave processors |
| 08/04/1992 | US5136496 Master/slave numerical control apparatus in which the master can identify types and order of the slaves |
| 08/04/1992 | US5136467 IC card adapter with card receptors in the sides of the housing |
| 08/04/1992 | US5136291 Transmitting binary data files using electronic mail |
| 08/04/1992 | CA1306071C Direct memory access controlled system |
| 08/04/1992 | CA1306068C Apparatus and method for servicing interrupts utilizing a pended bus |
| 07/29/1992 | EP0496535A2 Automatic device configuration for dockable computers |
| 07/29/1992 | EP0496390A2 Connection hold control system |
| 07/29/1992 | EP0496177A1 Method of transmitting data by buffer chaining between a host computer and a communication controller |
| 07/29/1992 | EP0294420B1 Data transfer circuit |
| 07/29/1992 | CN1063167A Personal computer with local memory expansion capability |
| 07/28/1992 | US5134706 Bus interface interrupt apparatus |
| 07/28/1992 | US5134699 Programmable burst data transfer apparatus and technique |
| 07/28/1992 | US5134691 Bidirectional communication and control network with programmable microcontroller interfacing digital ICs transmitting in serial format to controlled product |
| 07/28/1992 | US5134613 Two parety memory access arbitrator |
| 07/28/1992 | US5134311 Self-adjusting impedance matching driver |
| 07/25/1992 | CA2059878A1 Connection hold control system |
| 07/23/1992 | WO1992012599A1 Audio and video transmission and receiving system |
| 07/23/1992 | WO1992012486A1 Novel transaction system architecture |
| 07/23/1992 | WO1992012481A1 Wireless personal communication system |
| 07/23/1992 | WO1992012480A1 Transaction system emulator |
| 07/23/1992 | DE4037723A1 Transferring data from interfaces to processor controlling installation - using interrupt controller with priority arranged inputs from interface devices |
| 07/22/1992 | EP0495515A2 Method of assigning message identifiers in the data transmission network of an elevator system |
| 07/22/1992 | EP0315653B1 Remote services console for digital data processing system |
| 07/21/1992 | US5133078 Serial frame processing system in which validation and transfer of a frame's data from input buffer to output buffer proceed concurrently |
| 07/21/1992 | US5133071 Channel control method and apparatus |
| 07/21/1992 | US5133059 Computer with multiple processors having varying priorities for access to a multi-element memory |
| 07/21/1992 | US5133056 Interrupt controller |
| 07/21/1992 | US5133054 Data transmission apparatus for autonomously and selectively transmitting data to a plurality of transfer path |
| 07/21/1992 | US5133053 Interprocess communication queue location transparency |
| 07/21/1992 | US5133026 Computer input and character recognition system using facsimile |
| 07/21/1992 | US5132992 Audio and video transmission and receiving system |
| 07/21/1992 | US5132967 Single competitor arbitration scheme for common bus |
| 07/21/1992 | US5132962 Fault isolation and bypass reconfiguration unit |
| 07/21/1992 | US5132902 Method for automated process delay within a data processing system |
| 07/21/1992 | US5132898 System for processing data having different formats |
| 07/21/1992 | US5132827 Optical fibre communication link for connecting a peripheral device to a computer system |
| 07/21/1992 | CA1305560C Method and apparatus for interconnecting busses in a multibus computer system |
| 07/21/1992 | CA1305559C Increased bandwidth for multi-processor access of a common resource |
| 07/21/1992 | CA1305558C Interrupting node for providing interrupt requests to a pended bus |
| 07/15/1992 | EP0494447A1 High speed latch transceiver |
| 07/15/1992 | EP0494335A2 Maintaining compressed historical traffic statistics relative to local area networks |
| 07/14/1992 | US5131092 Communication system enabling programmable logic controllers access to host computer tasks and host computer access to programmable logic controllers without polling |
| 07/14/1992 | US5131089 Solid state disk drive emulation |
| 07/14/1992 | US5131085 High performance shared main storage interface |
| 07/14/1992 | US5131083 Method of transferring burst data in a microprocessor |
| 07/14/1992 | US5131082 Command delivery for a computing system for transfers between a host and subsystem including providing direct commands or indirect commands indicating the address of the subsystem control block |
| 07/14/1992 | US5131081 System having a host independent input/output processor for controlling data transfer between a memory and a plurality of i/o controllers |
| 07/14/1992 | US5130924 System for defining relationships among document elements including logical relationships of elements in a multi-dimensional tabular specification |
| 07/09/1992 | WO1992011744A1 Reception structure for adaptors of terminals belonging to a distributed data processing architecture |
| 07/09/1992 | WO1992011605A1 Neural network with daisy chain control |
| 07/09/1992 | DE4100056A1 Data communications between computer system and peripherals - detecting control address in address protocol, converting address, blocking normal data path and connecting to peripheral |
| 07/08/1992 | EP0494056A2 Dynamically partitionable and allocable bus structure |