| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 08/04/1998 | US5789946 Active pull down emitter coupled logic circuit |
| 08/04/1998 | US5789944 Asynchronous anticontention logic for bi-directional signals |
| 08/04/1998 | US5789943 V.35 network terminator |
| 08/04/1998 | US5789942 High speed signal level converting circuit having a reduced consumed electric power |
| 08/04/1998 | US5789941 ECL level/CMOS level logic signal interfacing device |
| 08/04/1998 | US5789940 Reduced complexity multiple resonant tunneling circuits for positive digit multivalued logic operations |
| 08/04/1998 | US5789939 Method for providing a plurality of hierarchical signal paths in a very high-density programmable logic device |
| 08/04/1998 | US5789938 Structure and method for reading blocks of data from selectable points in a memory device |
| 08/04/1998 | US5789937 Impedence self-adjusting driver circuit |
| 08/04/1998 | US5789779 IGFET circuit preventing parasitic diode current |
| 08/04/1998 | US5789770 Hexagonal architecture with triangular shaped cells |
| 07/30/1998 | WO1998033306A1 Method of using multisignal single unit and plural unit |
| 07/30/1998 | WO1998033278A1 Latch circuit |
| 07/30/1998 | WO1998033277A1 Field programmable processor arrays |
| 07/30/1998 | WO1998033276A1 Field programmable processor |
| 07/30/1998 | WO1998033275A1 Input buffer circuit, semiconductor integrated circuit, and board system |
| 07/30/1998 | WO1998033182A1 Data routing devices |
| 07/30/1998 | CA2279429A1 Latch circuit |
| 07/29/1998 | EP0855801A1 Non-blocking multiple phase clocking scheme for dynamic logic |
| 07/29/1998 | EP0855742A1 Semiconductor integrated circuit device produced from master slice and having operation mode easily changeable after selection on master slice |
| 07/29/1998 | EP0855105A1 Self-configuring bus |
| 07/29/1998 | EP0855104A1 Gatable level-pulling circuit |
| 07/29/1998 | CN1189258A Floor plan for scalable multiple level interconnect architecture |
| 07/29/1998 | CN1189013A Low-power consumption type semiconductor device |
| 07/28/1998 | US5787011 Low-power design techniques for high-performance CMOS circuits |
| 07/28/1998 | US5786723 Voltage switching circuit for a semiconductor memory device |
| 07/28/1998 | US5786720 5 volt CMOS driver circuit for driving 3.3 volt line |
| 07/28/1998 | US5786719 Mode setting circuit and mode setting apparatus used to select a particular semiconductor function |
| 07/28/1998 | US5786711 Data output buffer for use in a semiconductor memory device |
| 07/28/1998 | US5786710 Programmable I/O cell with data conversion capability |
| 07/28/1998 | US5786709 Integrated circuit output driver incorporating power distribution noise suppression circuitry |
| 07/28/1998 | US5786686 Low-power consumption type semiconductor device |
| 07/23/1998 | WO1998032229A1 Configurable logic block with and gate for efficient multiplication in fpgas |
| 07/23/1998 | WO1998032228A1 Low voltage interface circuit with a high voltage tolerance |
| 07/22/1998 | EP0854586A2 Quadrature spread spectrum signal demodulation |
| 07/22/1998 | EP0854578A2 Application specific integrated circuit (asic) having improved reset deactivation |
| 07/22/1998 | EP0854577A2 Semiconductor integrated circuit |
| 07/22/1998 | EP0853841A1 A clock signal frequency multiplier |
| 07/22/1998 | EP0853840A1 A semi-conductor integrated circuit |
| 07/22/1998 | CN1188569A Scalable multiple level interconnect architecture |
| 07/21/1998 | US5784575 Output driver that parks output before going tristate |
| 07/21/1998 | US5784313 Programmable logic device including configuration data or user data memory slices |
| 07/21/1998 | US5784241 Electromagnetic-noise protection circuit |
| 07/21/1998 | US5783963 ASIC with selectable output drivers |
| 07/21/1998 | US5783961 Inverted amplifying circuit |
| 07/21/1998 | US5783950 Phase comparator |
| 07/21/1998 | US5783949 Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories |
| 07/21/1998 | US5783948 Voltage elevation system |
| 07/21/1998 | US5783840 Universal quantum dot logic cell |
| 07/16/1998 | WO1998031103A1 Fpga two-turn routing structure with lane changing and minimum diffusion area |
| 07/16/1998 | WO1998031102A1 Reconfiguration method for programmable components during running time |
| 07/16/1998 | WO1998031101A1 Logical circuit where path transistor circuit and cmos circuit are combined, and its combination method |
| 07/15/1998 | EP0852848A1 Programmable logic device with configurable power supply |
| 07/15/1998 | CN1187717A Tuner for cable modem |
| 07/14/1998 | US5781765 System for data synchronization between two devices using four time domains |
| 07/14/1998 | US5781756 Programmable logic device with partially configurable memory cells and a method for configuration |
| 07/14/1998 | US5781062 Semiconductor integrated circuit |
| 07/14/1998 | US5781061 Current mirror circuit and signal processing circuit having improved resistance to current output terminal voltage variation |
| 07/14/1998 | US5781059 Driver circuit for semiconductor test system |
| 07/14/1998 | US5781056 Variable delay circuit |
| 07/14/1998 | US5781050 Open drain output driver having digital slew rate control |
| 07/14/1998 | US5781045 Method and apparatus for predriving a driver circuit for a relatively high current load |
| 07/14/1998 | US5781035 Dual-differential-pair emitter-coupled logic complementary-output circuit |
| 07/14/1998 | US5781034 For generating an output signal on a pad connected |
| 07/14/1998 | US5781033 Logic module with configurable combinational and sequential blocks |
| 07/14/1998 | US5781032 Programmable inverter circuit used in a programmable logic cell |
| 07/14/1998 | US5781031 Programmable logic array |
| 07/14/1998 | US5781030 Programmable uniform symmetrical distribution logic allocator for a high-density complex PLD |
| 07/14/1998 | US5781028 System and method for a switched data bus termination |
| 07/14/1998 | US5781025 Method for testing an electronic circuit by logically combining clock signals, and an electronic circuit provided with facilities for such testing |
| 07/09/1998 | WO1998029950A2 Internal voltage references output driver |
| 07/09/1998 | WO1998029949A1 Single-phase domino time borrowing logic with clocks at first and last stages and latch at last stage |
| 07/09/1998 | WO1998021859A3 Output buffer circuit |
| 07/09/1998 | DE19700045A1 Output buffer with high current control using CMOS technology |
| 07/09/1998 | DE19639635C1 CMOS-bus driver circuit for data bus system |
| 07/08/1998 | EP0800720A4 Substrate clamp for non-isolated integrated circuits |
| 07/08/1998 | CN1187073A Low power required input buffer |
| 07/08/1998 | CN1187071A Separate set/reset paths for time critical signals |
| 07/07/1998 | US5778439 Programmable logic device with hierarchical confiquration and state storage |
| 07/07/1998 | US5777944 Circuit and method for instruction controllable slewrate of bit line driver |
| 07/07/1998 | US5777887 FPGA redundancy |
| 07/07/1998 | US5777505 Circuit |
| 07/07/1998 | US5777497 CMOS output circuit with precharge circuit |
| 07/07/1998 | US5777496 Circuit for preventing more than one transistor from conducting |
| 07/07/1998 | US5777491 High-performance differential cascode voltage switch with pass gate logic elements |
| 07/07/1998 | US5777490 Circuitry and method for translating voltages |
| 07/07/1998 | US5777489 Field programmable gate array with integrated debugging facilities |
| 07/07/1998 | US5777488 Integrated circuit I/O node useable for configuration input at reset and normal output at other times |
| 07/07/1998 | US5777360 Hexagonal field programmable gate array architecture |
| 07/07/1998 | CA2006358C Process for preparing mono-n-alkylated polyazamacrocycles |
| 07/02/1998 | WO1998028848A1 Output driver for sub-micron cmos |
| 07/02/1998 | WO1998028782A2 Multi-bus programmable interconnect architecture |
| 07/02/1998 | DE19730745A1 Emitter-coupled logic circuit |
| 07/02/1998 | DE19718767A1 Output contact circuit using control signal for IC chip exchange |
| 07/02/1998 | DE19706069C1 Integrierte Buffer-Schaltung Integrated buffer circuit |
| 07/02/1998 | DE19654593A1 Umkonfigurierungs-Verfahren für programmierbare Bausteine zur Laufzeit Reconfiguration method for programmable devices at runtime |
| 07/01/1998 | EP0851588A1 Charge pump circuit for the frequency control loop of a frequency synthesizer |
| 07/01/1998 | EP0851587A2 MOS logic circuit |
| 07/01/1998 | EP0851586A1 Integrated circuit including an asymmetrizer |
| 07/01/1998 | EP0851584A2 Improvements in or relating to integrated circuits |