Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
04/2003
04/03/2003US20030062922 Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
04/03/2003US20030062920 Digital update scheme for adaptive impedance control of on-die input/output circuits
04/02/2003EP1297629A1 Buffer with compensating drive strength
04/02/2003EP0956646B1 Field programmable processor arrays
04/02/2003EP0712548B1 Architecture and interconnect scheme for programmable logic circuits
04/02/2003CN1407726A Driving circuit
04/02/2003CN1407725A Universal positive emitter coupling logic/low voltage differential command output structure
04/02/2003CN1407724A 半导体器件 Semiconductor devices
04/01/2003USRE38059 Semiconductor integrated logic circuit device using a pass transistor
04/01/2003US6542394 Field programmable processor arrays
04/01/2003US6542031 Switched IOH and IOL current sources for CMOS low-voltage PECL driver with self-timed pull-down current boost
04/01/2003US6542012 Circuit for driving gate of IGBT inverter
04/01/2003US6542011 Driver circuit, receiver circuit, and semiconductor integrated circuit device
04/01/2003US6542007 Inverter circuit
04/01/2003US6542006 Reset first latching mechanism for pulsed circuit topologies
04/01/2003US6542003 Circuit configuration and method for directly electrically isolated broadband transmission
04/01/2003US6542002 Hybrid power supply circuit and method for charging/discharging a logic circuit using the same
04/01/2003US6542000 Nonvolatile programmable logic devices
04/01/2003US6541998 Active termination circuit with an enable/disable
04/01/2003US6541997 Clockless impedance controller
04/01/2003US6541996 Dynamic impedance compensation circuit and method
04/01/2003US6541995 Circuit and method for driving signals to a receiver with terminators
03/2003
03/27/2003WO2003026131A2 Standard cell arrangement for a magneto-resistive component
03/27/2003WO2003025804A2 Structures and methods for selectively applying a well bias to portions of a programmable device
03/27/2003WO2003025784A2 Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations
03/27/2003WO2003025763A2 Functional pathway configuration at a system/ic interface
03/27/2003US20030061555 Semiconductor integrated circuit
03/27/2003US20030059997 Output buffer for a nonvolatile memory with optimized slew-rate control
03/27/2003US20030058732 Semiconductor memory device with an adaptive output driver
03/27/2003US20030058697 Programmable molecular device
03/27/2003US20030058060 Noise reduction high frequency circuit
03/27/2003US20030058046 Data receiver and method for receiving data using folded differential voltage sampler
03/27/2003US20030058032 Semiconductor integrated circuit and semiconductor memory having a voltage step-down circuit stepping external power supply voltage down to internal power supply voltage
03/27/2003US20030058023 Level shift circuit
03/27/2003US20030058019 Conditional clock buffer circuit
03/27/2003US20030058008 Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
03/27/2003US20030058007 Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation
03/27/2003US20030058005 Low-power output controlled circuit
03/27/2003US20030058002 Semiconductor integrated circuit device having power reduction mechanism
03/27/2003US20030058001 Fast, symmetrical XOR/XNOR gate
03/27/2003US20030058000 Full-swing source-follower leakage tolerant dynamic logic
03/27/2003US20030057999 Very low power, high performance universal connector for reconfigurable macro cell arrays
03/27/2003US20030057998 Circuit for reducing pin count of a semiconductor chip and method for configuring the chip
03/27/2003US20030057997 One cell programmable switch using non-volatile cell
03/27/2003US20030057996 Methods and apparatus for reconfiguring programmable devices
03/27/2003US20030057994 Electronic circuit with a driver circuit
03/27/2003US20030057775 Semiconductor integrated circuit and multi-chip package
03/26/2003EP1296154A2 Semiconductor integrated circuit
03/26/2003EP1295394A2 Block ram having multiple configurable write modes for use in a field programmable gate array
03/26/2003EP1116107B1 Method for executing individual algorithms by means of a reconfigurable circuit and device for carrying out such a method
03/26/2003EP0677191B1 Method and apparatus for transmitting nrz data signals across an isolation barrier disposed in an interface between adjacent devices on a bus
03/26/2003CN1405887A 半导体器件 Semiconductor devices
03/26/2003CN1104091C 时钟驱动器 Clock Driver
03/25/2003US6539535 Programmable logic device having integrated probing structures
03/25/2003US6539511 Semiconductor integrated circuit devices with test circuit
03/25/2003US6538500 Power efficient line driver with 4X supply voltage swing and active termination
03/25/2003US6538493 Semiconductor integrated circuit
03/25/2003US6538489 Clock distributing circuit in programmable logic device
03/25/2003US6538488 Clock buffer circuit having short propagation delay
03/25/2003US6538487 Electrical circuit having inverters being serially connected together in a cascade
03/25/2003US6538485 Dual tristate path output buffer control
03/25/2003US6538474 Digital interface with low power consumption
03/25/2003US6538473 High speed digital signal buffer and method
03/25/2003US6538472 Interface circuitry
03/25/2003US6538470 Devices and methods with programmable logic and digital signal processing regions
03/25/2003US6538469 Technique to test an integrated circuit using fewer pins
03/25/2003US6538468 Method and apparatus for multiple boot-up functionalities for a programmable logic device (PLD)
03/25/2003US6538467 Multi-access FIFO queue
03/25/2003US6538466 Buffer with stable trip point
03/25/2003US6538464 Slew rate control
03/20/2003WO2003024040A1 Differential line driver with on-chip termination
03/20/2003WO2003023965A2 Method and circuit designs for systematic adjustments in high-speed cmos circuits
03/20/2003US20030056160 Detecting and mitigating memory device latchup in a data processor
03/20/2003US20030056091 Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations
03/20/2003US20030056085 Unit for processing numeric and logic operations for use in central processing units (CPUS), multiprocessor systems, data-flow processors (DSPS), systolic processors and field programmable gate arrays (FPGAS)
03/20/2003US20030054960 Superconductive crossbar switch
03/20/2003US20030053335 Structures and methods for selectively applying a well bias to portions of a programmable device
03/20/2003US20030053273 Electronic device having a CMOS circuit
03/20/2003US20030052730 Semiconductor integrated circuit
03/20/2003US20030052725 Voltage translator
03/20/2003US20030052716 CMOS sequential logic configuration for an edge triggered flip-flop
03/20/2003US20030052715 Method and apparatus for mitigating the hysteresis effect in a sensing circuit
03/20/2003US20030052714 Enhanced domino circuit
03/20/2003US20030052713 Programmable logic device including multipliers and configurations thereof to reduce resource utilization
03/20/2003US20030052712 Electrically-programmable interconnect architecture for easily-configurable stacked circuit arrangements
03/20/2003US20030052710 Methods and apparatus for loading data into a plurality of programmable devices
03/20/2003US20030052709 Programmable logic devices with multi-standard byte synchronization and channel alignment for communication
03/20/2003US20030052707 Circuit and method for driving signals to a receiver with terminators
03/20/2003US20030052369 Semiconductor output circuit device
03/20/2003US20030052345 Semiconductor apparatus capable of preventing occurrence of multiple reflection, driving method, and setting method thereof
03/19/2003EP1294099A2 Programmable High-Speed I/O Interface
03/19/2003EP1294098A2 Scalable multiple level interconnect architecture
03/19/2003EP1294097A2 Input/output buffer supporting multiple I/O standards
03/19/2003EP1294094A2 Programmable logic device including multipliers and configurations thereof to reduce resource utilization
03/19/2003EP1293918A2 Methods and apparatus for reconfiguring programmable devices
03/19/2003EP1293077A2 A data transfer and management system
03/19/2003CN1404654A Level-shifter for extremely Low power supply
03/19/2003CN1404231A Antinoise and burst mode receiving equipment and method for recovering clock signal and its data
03/19/2003CN1404154A Semiconductor apparatus and producing method thereof
03/19/2003CN1404149A Semiconductor device with electrostatic discharge protective circuit
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