Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
11/2003
11/06/2003US20030206048 Data transmission system
11/06/2003US20030206046 Differential memory interface system
11/06/2003US20030206037 Monotonic dynamic static pseudo-NMOS logic circuits
11/06/2003US20030206036 Customizable and programmable cell array
11/05/2003EP1359668A1 Output buffer circuit
11/05/2003EP1359562A2 Predrive circuit, drive circuit and display device
11/05/2003EP1358531A2 Programmable logic device with decryption algorithm and decryption key
11/05/2003EP1358530A2 Programmable logic device with method of prreventing readback
11/05/2003EP1252561B1 Microprocessor resistant to power analysis
11/05/2003EP1222621B1 Integrated circuit and circuit arrangement for supplying an integrated circuit with electricity
11/05/2003EP1110320B1 Output driving circuit
11/05/2003CN2585488Y Multi-functional base pin circuit
11/05/2003CN2585487Y Wafer having even number stage output driving buffer circuit
11/04/2003US6643208 Semiconductor integrated circuit device having hierarchical power source arrangement
11/04/2003US6643110 Stress-follower circuit configuration
11/04/2003US6642771 Integrated XOR/summer/multiplexer for high speed phase detection
11/04/2003US6642758 Voltage, temperature, and process independent programmable phase shift for PLL
11/04/2003US6642748 Input circuit
11/04/2003US6642745 Semiconductor circuit and predischarge method of semiconductor circuit
11/04/2003US6642744 Customizable and programmable cell array
11/04/2003US6642743 System for rapid configuration of a programmable logic device
11/04/2003US6642742 Method and apparatus for controlling output impedance
11/04/2003US6642740 Programmable termination circuit and method
11/03/2003CA2403522A1 Superconducting quantum-bit device based on josephson junctions
10/2003
10/30/2003WO2003090357A1 Interfaces between semiconductor circuitry and transpinnor-based circuitry
10/30/2003WO2003090341A1 Circuitry to provide a low power input buffer
10/30/2003WO2003090229A2 Memory cells enhanced for resistance to single event upset
10/30/2003WO2003089945A1 Circuit part comprising at least two magnetoresistive layer elements with inverted output signals
10/30/2003WO2002071611A3 Monotonic dynamic-static pseudo-nmos logic circuit and method of forming a logic gate array
10/30/2003WO2002071249A8 Method and devices for treating and/or processing data
10/30/2003WO2002071196A8 Methods and devices for treating and processing data
10/30/2003WO2002007400A9 Digital interface with low power consumption
10/30/2003US20030204828 Method for calculation of cell delay time and method for layout optimization of semiconductor integrated circuit
10/30/2003US20030201918 Method and apparatus for adaptive bus coding for low power deep sub-micron designs
10/30/2003US20030201820 Bias voltage generating circuit and semiconductor integrated circuit device
10/30/2003US20030201817 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
10/30/2003US20030201811 Method and device for symmetrical slew rate calibration
10/30/2003US20030201807 Power on reset circuit
10/30/2003US20030201804 Programmable dual-drive strength output buffer with a shared boot circuit
10/30/2003US20030201800 Latch-type level converter and receiver circuit accurately amplifying low-amplitude signals and receiving common-mode input signals higher than a supply voltage
10/30/2003US20030201799 Output circuit capable of transmitting signal with optimal amplitude and optimal common-mode voltage at receiver circuit
10/30/2003US20030201798 General-purpose logic module and cell using the same
10/30/2003US20030201797 Method and apparatus for asynchronously controlling a high-capacity domino pipeline
10/30/2003US20030201796 Method and apparatus for asynchronously controlling domino logic gates
10/30/2003US20030201795 Tileable field-programmable gate array architecture
10/30/2003US20030201794 Programmable logic device with hierarchical interconnection resources
10/30/2003US20030201793 Line segmentation in programmable logic devices having redundancy circuitry
10/30/2003US20030201792 High density antifuse based partitioned FPGA architecture
10/29/2003EP1357388A2 Input/output characterization register (chain) for an integrated circuit
10/29/2003EP1356616A2 Double data rate flip-flop
10/29/2003EP1356590A2 Sub-micron high input voltage tolerant input output (i/o) circuit
10/29/2003EP1212833B1 Driver circuit and method for operating a driver circuit
10/29/2003CN1452318A Differential output structure with decreased bias under single input
10/29/2003CN1452242A Chip terminating device in semiconductor IC and controlling method thereof
10/29/2003CN1452148A Predriving circuit, driving circuit and display apparatus
10/29/2003CN1452080A Semiconductor integrated circuit
10/28/2003US6639845 Data holding circuit having backup function
10/28/2003US6639774 Damping circuit for a two-wire bus system
10/28/2003US6639455 Semiconductor integrated circuit device
10/28/2003US6639454 Multiple circuit blocks with interblock control and power conservation
10/28/2003US6639450 Enhanced conductivity body biased PMOS driver
10/28/2003US6639445 Semiconductor integrated circuit
10/28/2003US6639429 Method for clock control of half-rail differential logic
10/28/2003US6639428 Method and system for dynamically clocking digital systems based on power usage
10/28/2003US6639427 High-voltage switching device and application to a non-volatile memory
10/28/2003US6639424 Combined dynamic logic gate and level shifter and method employing same
10/28/2003US6639423 Current mode driver with variable termination
10/28/2003US6639422 Multi-clock integrated circuit with clock generator and bi-directional clock pin arrangement
10/28/2003US6638360 Methods for the separation of isomers
10/23/2003WO2003088488A2 Circuit arrangement and method for generating a dual-rail output signal
10/23/2003WO2003088289A2 Dual threshold voltage and low swing domino logic circuits
10/23/2003WO2003088071A2 High-performance hybrid processor with configurable execution units
10/23/2003WO2002097638A3 An integrated circuit arrangement with feature control
10/23/2003WO2002041146A3 Instruction processor systems and methods
10/23/2003WO2002021693A3 Field programmable gate array and microcontroller system-on-a-chip
10/23/2003US20030200495 Semiconductor integrated circuit and its design methodology
10/23/2003US20030200045 Input/output characterization chain for an integrated circuit
10/23/2003US20030199153 Method of producing SI-GE base semiconductor devices
10/23/2003US20030198343 Combinational circuit, encryption circuit, method for constructing the same and program
10/23/2003US20030198088 Voltage detection circuit and method for semiconductor memory devices
10/23/2003US20030197696 Predrive circuit, drive circuit and display device
10/23/2003US20030197551 Potential generating circuit capable of correctly controlling output potential
10/23/2003US20030197547 Semiconductor integrated circuit device and microcomputer
10/23/2003US20030197542 Voltage island communications circuits
10/23/2003US20030197539 Differential output structure with reduced skew for a single input
10/23/2003US20030197530 Semiconductor logical operation circuit
10/23/2003US20030197527 Method and apparatus for universal program controlled bus architecture
10/23/2003US20030197526 Output buffer circuit
10/23/2003US20030197525 On-chip termination apparatus in semiconductor integrated circuit, and method for controlling the same
10/23/2003US20030197218 Reducing substrate hot electrodes
10/22/2003EP1355426A1 Multi-bit digital input using a single pin
10/22/2003EP1355423A2 Dynamic to static converter with noise suppression
10/22/2003EP1355362A1 Semiconductor device
10/22/2003EP1355315A2 Voltage detection circuit and method for semiconductor memory devices
10/22/2003EP1354405A2 Depopulated programmable logic array
10/22/2003EP1354404A2 Tileable field-programmable gate array architecture
10/22/2003EP1354403A2 Sub-micron high input voltage tolerant input output (i/o) circuit which accommodates large power supply variations
10/22/2003EP0803148B1 Method for switching high voltages on a semiconductor chip
10/22/2003CN1451140A Method and circuit for providing interface signals setween integrated circuits
10/21/2003US6637017 Real time programmable feature control for programmable logic devices
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