Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
09/2003
09/17/2003EP0807333B1 Low voltage logic circuit
09/17/2003CN1443310A 异步复位电路测试 Asynchronous reset circuit test
09/17/2003CN1442954A Bus buffer circuit containing logic circuit
09/17/2003CN1121757C Signal conversion apparatus and application on LST circuit
09/16/2003US6621329 Semiconductor device
09/16/2003US6621327 Substrate voltage selection circuit
09/16/2003US6621325 Structures and methods for selectively applying a well bias to portions of a programmable device
09/16/2003US6621322 Voltage generating circuit, level shift circuit and semiconductor device
09/16/2003US6621310 Reducing power consumption variability of precharge-pulldown busses
09/16/2003US6621308 Supply voltage compensation circuit for high speed LVDS predrive
09/16/2003US6621306 Random logic circuit
09/16/2003US6621305 Partial swing low power CMOS logic circuits
09/16/2003US6621301 Pass-driver circuit for two-conductor bus-system
09/16/2003US6621300 System and method for improving speed of operation of integrated circuits
09/16/2003US6621299 Control circuit for power
09/16/2003US6621298 Variable grain architecture for FPGA integrated circuits
09/16/2003US6621297 Semiconductor device malfunction preventive circuit
09/16/2003US6621296 FPGA lookup table with high speed read decorder
09/16/2003US6621295 Reconfigurable priority encoding
09/16/2003US6621294 Number of pads of a semiconductor chip can be greatly reduced
09/16/2003US6621293 Integrated circuit arrangement with feature control
09/16/2003US6621292 Semiconductor integrated circuits with power reduction mechanism
09/16/2003US6621144 Data receiver gain enhancement
09/12/2003WO2003075477A2 High speed configurable transceiver architecture
09/12/2003WO2003075464A1 Line driver with reduced power consumption
09/12/2003WO2003075463A1 Leakage reduction circuit
09/12/2003WO2003075460A2 Low power dynamic logic gate with full voltage swing operation
09/12/2003WO2003075138A1 Low jitter clock for a multi-gigabit transceiver on a field programmable gate array
09/12/2003WO2002044876A3 Programmable logic device with decryption algorithm and decryption key
09/12/2003WO2002044875A3 Programmable logic device with method of preventing readback
09/12/2003CA2478023A1 High speed configurable transceiver architecture
09/11/2003US20030172364 Software programmable multiple function integrated circuit module
09/11/2003US20030172363 Utilization of unused IO block for core logic functions
09/11/2003US20030172360 Method and system for compiling circuit designs
09/11/2003US20030172359 Circuit arrangement
09/11/2003US20030171909 Logic emulator
09/11/2003US20030169605 Device and method for inhibiting power fluctuation
09/11/2003US20030169225 Amplitude conversion circuit for converting signal amplitude
09/11/2003US20030169081 Impedance controlled double data rate input buffer
09/11/2003US20030169076 Input buffer circuit and semiconductor memory device
09/11/2003US20030169075 I/O buffer having a protection circuit for handling different voltage supply levels
09/11/2003US20030169073 Logic circuitry-implemented bus buffer
09/11/2003US20030169071 Switch matrix circuit, logical operation circuit, and switch circuit
09/11/2003US20030169069 Multiple finger off chip driver (OCD) with single level translator
09/11/2003US20030169068 Input termination with high impedance at power off
09/10/2003EP1342319A1 Integrated circuit with output drivers
09/10/2003EP1342163A2 Method and apparatus for communicating with a host
09/10/2003CN2572672Y Digital value input circuit
09/10/2003CN2572671Y Relay digital value output circuit
09/10/2003CN1441996A 快速切换输入缓冲器 Fast switching input buffer
09/09/2003US6618233 Double triggering mechanism for achieving faster turn-on
09/09/2003US6618083 Mismatch-independent reset sensing for CMOS area array sensors
09/09/2003US6617925 Method and apparatus for gain compensation and control in low voltage differential signaling applications
09/09/2003US6617916 Semiconductor integrated circuit
09/09/2003US6617907 Voltage translator
09/09/2003US6617903 Inverter circuit having an improved slew rate
09/09/2003US6617902 Semiconductor memory and holding device
09/09/2003US6617896 Complementary signal generation circuit
09/09/2003US6617895 Method and device for symmetrical slew rate calibration
09/09/2003US6617884 Fast locking phase frequency detector
09/09/2003US6617881 Semiconductor integrated circuit
09/09/2003US6617880 Method and apparatus for a low power, multi-mode GTL I/O buffer utilizing midrail I/O buffer pad clamping
09/09/2003US6617878 Voltage level shifter and display device
09/09/2003US6617877 Variable data width operation in multi-gigabit transceivers on a programmable logic device
09/09/2003US6617876 Structures and methods for distributing high-fanout signals in FPGAs using carry multiplexers
09/09/2003US6617875 Programmable multi-standard I/O architecture for FPGAs
09/09/2003US6617873 Semiconductor integrated circuit and testing method thereof
09/04/2003WO2003073620A1 Floor planning for programmable gate array having embedded fixed logic circuitry
09/04/2003WO2003073619A2 Method for controlling the mode of an electronic application
09/04/2003WO2003073617A1 Amplitude converting circuit
09/04/2003WO2003073614A1 Circuit for accelerating the transitioning edge of a signal on a bidirectional bus
09/04/2003WO2003073470A2 Methods and systems for reducing power-on failures of integrated circuits
09/04/2003WO2003073096A1 Oligonucleotide-based logic gates and molecular networks
09/04/2003WO2002046936A8 Method and apparatus for communicating with a host
09/04/2003WO2001093491A3 High frequency network transmitter
09/04/2003US20030167439 Data integrity error handling in a redundant storage array
09/04/2003US20030164811 Flat panel display including transceiver circuit for digital interface
09/04/2003US20030164723 Output buffer circuit
09/04/2003US20030164722 System and method for compensating for the effects of process, voltage, and temperature variations in a circuit
09/04/2003US20030164697 Inductive proximity sensor and related methods
09/03/2003EP1341307A1 Logic circuit with compensation for the effects of process, voltage, and temperature variations
09/03/2003EP1123556A4 Fuse circuit having zero power draw for partially blown condition
09/03/2003CN1440120A Driving circuit with low current loss
09/03/2003CN1120574C Latch circuit
09/03/2003CN1120429C Data bus-line
09/02/2003US6615229 Dual threshold voltage complementary pass-transistor logic implementation of a low-power, partitioned multiplier
09/02/2003US6615027 Method and circuit for providing interface signals between integrated circuits
09/02/2003US6614703 Method and system for configuring integrated systems on a chip
09/02/2003US6614699 Booster circuit for raising voltage by sequentially transferring charges from input terminals of booster units to output terminals thereof in response to clock signals having different phases
09/02/2003US6614266 Semiconductor integrated circuit
09/02/2003US6614264 Method for increasing the load capacity of full-rail differential logic
09/02/2003US6614262 Failsafe interface circuit with extended drain devices
09/02/2003US6614261 Interconnection and input/output resources for programable logic integrated circuit devices
09/02/2003US6614260 System and method for dynamic modification of integrated circuit functionality
09/02/2003US6614259 Configuration memory integrated circuit
09/02/2003US6614258 Field-programmable dynamic logic array
09/02/2003US6614257 Logic architecture for single event upset immunity
09/02/2003US6614084 Magnetic materials
08/2003
08/28/2003WO2003071812A2 Method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time
08/28/2003WO2003071681A1 Integrated circuit having reduced substrate bounce
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