| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 02/17/2004 | US6693464 Low-voltage current mode logic circuits and methods |
| 02/17/2004 | US6693463 Current mode device and an arrangement |
| 02/17/2004 | US6693462 Low power dynamic logic gate with full voltage swing and two phase operation |
| 02/17/2004 | US6693461 Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipation |
| 02/17/2004 | US6693458 Apparatus for an optimized high speed comparator |
| 02/17/2004 | US6693457 Ultra high speed flip-flop |
| 02/17/2004 | US6693456 Interconnection network for a field programmable gate array |
| 02/17/2004 | US6693455 Programmable logic device including multipliers and configurations thereof to reduce resource utilization |
| 02/17/2004 | US6693454 Distributed RAM in a logic array |
| 02/17/2004 | US6693453 Re-programmable logic array |
| 02/17/2004 | US6693452 Floor planning for programmable gate array having embedded fixed logic circuitry |
| 02/17/2004 | US6693451 Input/output buffer capable of supporting a multiple of transmission logic buses |
| 02/17/2004 | US6693450 Dynamic swing voltage adjustment |
| 02/12/2004 | WO2004014065A2 System of finite state machines |
| 02/12/2004 | WO2004013965A1 Superconducting driver circuit |
| 02/12/2004 | WO2003003582A3 Low power operation mechanism and method |
| 02/12/2004 | WO2002069498A3 Rapid single flux quantum programmable gate array |
| 02/12/2004 | WO2002037679A3 Transmitter circuit comprising timing deskewing means |
| 02/12/2004 | US20040030999 Method and system for debugging using replicated logic |
| 02/12/2004 | US20040029313 Self-determining electronic control circuit |
| 02/12/2004 | US20040027902 Semiconductor device with reduced current consumption in standby state |
| 02/12/2004 | US20040027899 Magnetic logic elements |
| 02/12/2004 | US20040027862 Input buffer circuit of a synchronous semiconductor memory device |
| 02/12/2004 | US20040027265 BiCMOS latches with npn control devices for current limiting of npn regeneration devices |
| 02/12/2004 | US20040027179 Dual mode data output buffers and methods of operating the same |
| 02/12/2004 | US20040027178 Signal buffer for high-speed signal transmission and signal line driving circuit including the same |
| 02/12/2004 | US20040027177 Semiconductor integrated circuit |
| 02/12/2004 | US20040027176 Method and related circuitry for buffering output signals of a chip with even number driving circuits |
| 02/12/2004 | US20040027173 Multiple circuit blocks with interblock control and power conservation |
| 02/12/2004 | US20040027168 Method for increasing the load capacity of clocked half-rail differential logic |
| 02/12/2004 | US20040027167 Data transfer device for transferring data between blocks of different clock domains |
| 02/12/2004 | US20040027164 Clocked half-rail differential logic with sense amplifier |
| 02/12/2004 | US20040027163 Low power low voltage transistor-transistor logic I/O driver |
| 02/12/2004 | US20040027161 Method and circuit for reducing HCI stress |
| 02/12/2004 | US20040027160 Switchable power domains for 1.2V and 3.3V pad voltages |
| 02/12/2004 | US20040027159 5 Volt tolerant IO scheme using low-voltage devices |
| 02/12/2004 | US20040027157 Semiconductor integrated circuit |
| 02/12/2004 | US20040027156 Configurable cell for customizable logic array device |
| 02/12/2004 | US20040027154 Nanoelectronic devices |
| 02/12/2004 | US20040027153 Semiconductor integrated circuit and data processing system |
| 02/12/2004 | US20040027152 System and method for transmission-line termination by signal cancellation, and applications thereof |
| 02/12/2004 | US20040026793 Transceiver having shadow memory facilitating on-transceiver collection and communication of local parameters |
| 02/12/2004 | US20040026751 Semiconductor integrated circuit device |
| 02/11/2004 | EP1388952A1 Transceiver having shadow memory facilitating on-transceiver collection and communication of local parameters |
| 02/11/2004 | EP1388941A1 Field programmable device with dual-mode clock |
| 02/11/2004 | CN1475067A Active terminating device with optional line-receiving and line-driving capabilities |
| 02/11/2004 | CN1474567A 数据传送装置 Data transfer means |
| 02/11/2004 | CN1474510A 半导体集成电路 The semiconductor integrated circuit |
| 02/11/2004 | CN1474507A Output and input circuit, electronic circuit, multipath multiplexer and de-multiplexer |
| 02/11/2004 | CN1138195C Method and circuit device for processing digital signal |
| 02/10/2004 | US6691267 Technique to test an integrated circuit using fewer pins |
| 02/10/2004 | US6690744 Digital line driver circuit |
| 02/10/2004 | US6690605 Logic signal level converter circuit and memory data output buffer using the same |
| 02/10/2004 | US6690227 Charge pump circuit for use in high voltage generating circuit |
| 02/10/2004 | US6690222 Input pad with improved noise immunity and output characteristics |
| 02/10/2004 | US6690211 Impedance matching circuit |
| 02/10/2004 | US6690207 Power efficient emitter-coupled logic circuit |
| 02/10/2004 | US6690206 Semiconductor integrated circuit device |
| 02/10/2004 | US6690205 Enhanced domino circuit |
| 02/10/2004 | US6690204 Limited switch dynamic logic circuit |
| 02/10/2004 | US6690203 Method and apparatus for a failure-free synchronizer |
| 02/10/2004 | US6690200 Driving circuit for transmission lines |
| 02/10/2004 | US6690198 Repeater with reduced power consumption |
| 02/10/2004 | US6690195 Driver circuitry for programmable logic devices |
| 02/10/2004 | US6690194 Function block architecture for gate array |
| 02/10/2004 | US6690192 Current-compensated CMOS output buffer adjusting edge rate for process, temperature, and Vcc variations |
| 02/10/2004 | US6690191 Bi-directional output buffer |
| 02/05/2004 | WO2003100974A3 Pull up for high speed structures |
| 02/05/2004 | WO2003025804A3 Structures and methods for selectively applying a well bias to portions of a programmable device |
| 02/05/2004 | US20040025135 Structures and methods for selectively applying a well bias to portions of a programmable device |
| 02/05/2004 | US20040025074 Circuits and methods for high-capacity asynchronous pipeline |
| 02/05/2004 | US20040023620 Interface between digital and analog circuits |
| 02/05/2004 | US20040022005 Radiation-hard circuit |
| 02/05/2004 | US20040021652 Display element drive circuit and display device |
| 02/05/2004 | US20040021509 Circuitry to provide a low power input buffer |
| 02/05/2004 | US20040021501 Low-leakage integrated circuits and dynamic logic circuits |
| 02/05/2004 | US20040021496 Level shifter and flat panel display |
| 02/05/2004 | US20040021491 Apparatus for increasing slew rate |
| 02/05/2004 | US20040021487 Switching aid circuit for a logic circuit |
| 02/05/2004 | US20040021485 Semiconductor integrated circuit and circuit designating system |
| 02/05/2004 | US20040021484 Reducing short circuit power in cmos inverter circuits |
| 02/05/2004 | US20040021481 Method and circuit for producing control signal for impedance matching |
| 02/05/2004 | DE19751990B4 Datenausgangspuffer für eine Speichereinrichtung Data output buffer for a memory device |
| 02/05/2004 | DE10212640B4 Logische Bauteile aus organischen Feldeffekttransistoren Logical components of organic field-effect transistors |
| 02/04/2004 | EP1387494A1 CMOS circuits with protection for a single event upset |
| 02/04/2004 | EP1387491A2 Level shifter and flat panel display |
| 02/04/2004 | EP1386402A1 Modified repetitive cell matching technique for integrated circuits |
| 02/04/2004 | EP1386398A2 Antifuse reroute of dies |
| 02/04/2004 | EP1386397A1 Logic circuit with single event upset immunity |
| 02/04/2004 | EP1386284A2 Evolutionary programming of configurable logic devices |
| 02/04/2004 | EP1386247A2 User configurable on-chip memory system |
| 02/04/2004 | CN1472810A Semiconductor integrated circuits |
| 02/04/2004 | CN1472806A Method for forming semiconductor device and its structure |
| 02/04/2004 | CN1472717A Electric level shifter and panel display device |
| 02/04/2004 | CN1472623A Block interface circuit and systemic large integrated circuit |
| 02/03/2004 | US6687788 Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.) |
| 02/03/2004 | US6687166 Bus interface circuit and receiver circuit |
| 02/03/2004 | US6687165 Temperature-compensated output buffer circuit |
| 02/03/2004 | US6686899 Display device having an improved voltage level converter circuit |
| 02/03/2004 | US6686779 Driver circuit for differentially outputting data from internal circuitry of an LSI to outside the LSI |