Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
11/2003
11/25/2003US6654310 Semiconductor memory device with an adaptive output driver
11/25/2003US6654305 System LSI having a substrate-bias generation circuit with a substrate-bias control-value storage unit
11/25/2003US6653890 Well bias control circuit
11/25/2003US6653884 Input interface circuit for semiconductor integrated circuit device
11/25/2003US6653882 Output drivers for IC
11/25/2003US6653878 Low-power output controlled circuit
11/25/2003US6653873 Large loading driver circuit with high speed and low crowbar current
11/25/2003US6653868 Semiconductor integrated circuit, method and program for designing the semiconductor integrated circuit
11/25/2003US6653866 Domino logic with output predischarge
11/25/2003US6653864 Interface
11/25/2003US6653862 Use of dangling partial lines for interfacing in a PLD
11/25/2003US6653861 Multi-level routing structure for a programmable interconnect circuit
11/25/2003US6653860 Enhanced macrocell module having expandable product term sharing capability for use in high density CPLD architectures
11/25/2003US6653693 Semiconductor integrated circuit device
11/25/2003CA2321051C Clock stretcher and level shifter with small component count and low power consumption
11/20/2003WO2003096537A1 Cross point switch with serializer and deserializer functions
11/20/2003WO2002089133A3 Data integrity error handling in a redundant storage array
11/20/2003WO2002047339A3 Output driver circuit with current detection
11/20/2003US20030217307 Error detection in dynamic logic circuits
11/20/2003US20030216088 Buffer for contact circuit
11/20/2003US20030214772 Protection circuit against voltage or current spikes, and clock circuit using a protection circuit of this kind
11/20/2003US20030214477 Level shifter circuit and display device provided therewith
11/20/2003US20030214342 IO clamping circuit method utilizing output driver transistors
11/20/2003US20030214337 Latch circuit
11/20/2003US20030214328 Semiconductor device having input buffers to which internally-generated reference voltages are applied
11/20/2003US20030214327 Bulk input differential logic circuit
11/20/2003US20030214326 Distributed dynamically optimizable processing communications and storage system
11/20/2003US20030214325 Increasing drive strength and reducing propagation delays through the use of feedback
11/20/2003US20030214324 Function block architecture for gate array
11/20/2003US20030214323 General-purpose logic cell, general-purpose logic cell array using the same, and ASIC using general-purpose logic cell array
11/20/2003US20030214322 Distributed ram in a logic array
11/20/2003US20030214321 Architecture for programmable logic device
11/20/2003US20030214320 Semiconductor device and manufacturing method for the same
11/20/2003US20030214018 Semiconductor integrated circuit device
11/20/2003US20030213972 Semiconductor device used in two systems having different power supply voltages
11/19/2003EP1363402A2 Semiconductor device and manufacturing method for the same
11/19/2003EP1363401A1 Input buffers with common internal reference voltage
11/19/2003EP1363210A1 Design method for gate array integrated circuit
11/19/2003EP1362423A1 Self-terminating current mirror transceiver logic
11/19/2003EP1222739B1 Reconfigurable gate array
11/19/2003CN2587109Y FE transistor digital quantity output circuit
11/19/2003CN1457548A Interface circuit for differential signal
11/18/2003US6650174 Active pullup circuitry for open-drain signals
11/18/2003US6650171 Low power operation mechanism and method
11/18/2003US6650167 Multi-level/single ended input level shifter circuit
11/18/2003US6650158 Ferroelectric non-volatile logic elements
11/18/2003US6650149 Latched active fail-safe circuit for protecting a differential receiver
11/18/2003US6650145 Circuits and systems for limited switch dynamic logic
11/18/2003US6650142 Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use
11/18/2003US6650141 High speed interface for a programmable interconnect circuit
11/18/2003US6650140 Programmable logic device with high speed serial interface circuitry
11/18/2003US6650139 Modular collection of spare gates for use in hierarchical integrated circuit design process
11/18/2003US6649476 Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate array
11/18/2003CA2302939C Variable impedance data transmission device
11/13/2003WO2003094250A2 Superconducting quantum bit device with josephson junctions
11/13/2003WO2003065341A3 Apparatus and method for interfacing a digital video signal having a tdms format with a plurality digital video interface receivers
11/13/2003US20030212979 Depopulated programmable logic array
11/13/2003US20030212977 Design method for gate array integrated circuit
11/13/2003US20030212930 Clock data recovery circuitry associated with programmable logic device circuitry
11/13/2003US20030212924 Software development test case analyzer and optimizer
11/13/2003US20030210085 System and method for implementing a skew-tolerant true-single-phase-clocking flip-flop
11/13/2003US20030210079 Input/output buffer having reduced skew and methods of operation
11/13/2003US20030210075 Semiconductor integrated circuit capable of high-speed circuit operation
11/13/2003US20030210074 Voltage output differential (VOD) correction circuit for differential drivers
11/13/2003US20030210073 Interconnection and input/output resources for programmable logic integrated circuit devices
11/13/2003US20030210072 Architecture and interconnect scheme for programmable logic circuits
11/13/2003US20030210071 Cross point switch with serializer and deserializer functions
11/13/2003US20030210070 Internal bus termination technique for integrated circuits with local process/voltage/temperature compensation
11/13/2003US20030210021 Switch mode power supply and driving method for efficient RF amplification
11/12/2003EP1361660A2 Electronic circuit with at least one input for selecting a state of the electronic circuit
11/12/2003EP1360766A1 High -speed output driver
11/12/2003EP1360765A2 Buffers with reduced voltage input/output signals
11/12/2003EP0878054B1 Energy economized pass-transistor logic circuit and full adder using the same
11/12/2003EP0780984B1 Output circuit and electronic device using the circuit
11/12/2003CN1455958A Semiconductor device
11/12/2003CN1127769C Elimination of parasitic double-pole effect of insulator substrate epitaxial silicon
11/11/2003US6646952 Semiconductor circuit and semiconductor device
11/11/2003US6646950 High speed decoder for flash memory
11/11/2003US6646918 Semiconductor level shifter circuit
11/11/2003US6646490 Bipolar breakdown enhancement circuit for tri-state output stage
11/11/2003US6646486 Semiconductor integrated circuit
11/11/2003US6646483 Output buffer circuit for reducing variation of slew rate due to variation of PVT and load capacitance of output terminal, and semiconductor device including the same
11/11/2003US6646482 Variable drive current driver circuit
11/11/2003US6646474 Clocked pass transistor and complementary pass transistor logic circuits
11/11/2003US6646473 Multiple supply voltage dynamic logic
11/11/2003US6646471 Signal transfer circuit
11/11/2003US6646467 PCI-compatible programmable logic devices
11/11/2003US6646466 Interface scheme for connecting a fixed circuitry block to a programmable logic core
11/11/2003US6646465 Programmable logic device including bi-directional shift register
11/11/2003US6646464 Data hold circuit, a semiconductor device and a method of designing the same
11/06/2003WO2003071812A3 Method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time
11/06/2003WO2003010631A3 Hierarchical multiplexer-based integrated circuit interconnect architecture for scalability and automatic generation
11/06/2003WO2003005583A3 A reconfigurable analog cell and an arrangement comprising a plurality of such cell
11/06/2003WO2002075926A3 Antifuse reroute of dies
11/06/2003WO2002071209A3 Evolutionary programming of configurable logic devices
11/06/2003WO2002059759A3 Spatially filtered data bus drivers and receivers and method of operating same
11/06/2003WO2002027941A3 Digital to analog converter.
11/06/2003US20030208668 Single-ended memory interface system
11/06/2003US20030207766 Charge as a first principal degree of freedom assigned to writing and a phase as a second principal degree of freedom assigned to reading. The device comprises a Cooper-pair box comprising first and second Josephson junctions defining a
11/06/2003US20030206051 Global voltage buffer for voltage islands
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