Patents
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
12/2003
12/10/2003EP1370000A2 Programmable logic device circuit and method of fabricating same
12/10/2003EP1369999A1 Level shifter circuit with single ended input
12/10/2003EP1369998A1 Current switching circuit
12/10/2003EP1369997A2 Input/output buffer
12/10/2003EP1368672A2 A scan test system and method for manipulating logic values that remain constant during normal operations
12/10/2003CN1461526A Inductive proximity sensor and related methods
12/10/2003CN1461108A Semiconductor device suitable for cut-off and turn-on of power supply
12/10/2003CN1460987A Electrical level shifting circuit and display device including it
12/10/2003CN1130830C Integrated circuit device
12/10/2003CN1130829C Logic synthesizing method, semiconductor integrated circuit and operational circuit
12/09/2003US6662285 User configurable memory system having local and global memory blocks
12/09/2003US6661812 Bidirectional bus for use as an interconnect routing resource
12/09/2003US6661733 Dual-port SRAM in a programmable logic device
12/09/2003US6661729 Semiconductor device having test mode
12/09/2003US6661696 Ferroelectric random access memory configurable output driver circuit
12/09/2003US6661277 Enhanced conductivity body biased PMOS driver
12/09/2003US6661274 Level converter circuit
12/09/2003US6661268 Charge compensation control circuit and method for use with output driver
12/09/2003US6661260 Output circuit of semiconductor circuit with power consumption reduced
12/09/2003US6661259 Driver circuit
12/09/2003US6661257 Method for clocking charge recycling differential logic
12/09/2003US6661256 Race logic circuit
12/09/2003US6661255 Interface circuit
12/09/2003US6661254 Programmable interconnect circuit with a phase-locked loop
12/09/2003US6661250 Programmable impedance control circuit
12/09/2003US6661218 High voltage detector
12/04/2003WO2003100977A1 Distributed ram in a logic array
12/04/2003WO2003100976A1 Circuit for providing a predetermined potential at an output terminal of a powered-down logic circuit
12/04/2003WO2003100974A2 Pull up for high speed structures
12/04/2003WO2003100650A1 Reprogrammable hardware for examining network streaming data to detect redefinable patterns and define responsive processing
12/04/2003WO2002071196A3 Methods and devices for treating and processing data
12/04/2003WO2002056180A3 User configurable on-chip memory system
12/04/2003US20030226083 Self-synchronous logic circuit having test function and method of testing self-synchronous logic circuit
12/04/2003US20030225943 Input/output device having linearized output response
12/04/2003US20030223298 Efficient latch array initialization
12/04/2003US20030223295 Field programmable gate array with a variably wide word width memory
12/04/2003US20030222705 Output circuit device for clock signal distribution in high-speed signal transmission
12/04/2003US20030222700 Level shifter
12/04/2003US20030222699 Level shifter
12/04/2003US20030222697 Inverter circuit
12/04/2003US20030222692 Correction circuit, delay circuit, and ring oscillator circuit
12/04/2003US20030222686 Semiconductor integrated circuit device
12/04/2003US20030222684 Input/output buffer
12/04/2003US20030222683 Output driver having dynamic impedance control
12/04/2003US20030222682 Cascode stage input/output device
12/04/2003US20030222679 Voltage conversion circuit and semiconductor device
12/04/2003US20030222676 Programmable array logic circuit whose product and input line junctions employ single bit non-volatile ferromagnetic cells
12/04/2003US20030222675 Programmable Array logic Circuit macrocell using ferromagnetic memory cells
12/04/2003US20030222674 Electronic circuit device and electronic device package
12/04/2003US20030222309 Programmable logic device circuit and method of fabricating same
12/04/2003US20030222307 Device for reducing the effects of leakage current within electronic devices
12/04/2003US20030222285 Semiconductor device and system
12/04/2003CA2485076A1 Reprogrammable hardware for examining network streaming data to detect redefinable patterns and define responsive processing
12/03/2003EP1367718A2 Voltage conversion circuit and semiconductor device
12/03/2003EP1366570A1 In service programmable logic arrays with ultra thin vertical body transistors
12/03/2003EP1366495A1 High speed signal path and method
12/03/2003EP1196995B1 Tristate circuit for power up conditions
12/03/2003CN2590282Y Analog quantity output circuit
12/03/2003CN2590281Y Multipath logic signal generator
12/03/2003CN1459796A Semiconductor device for use in two systems with different power voltages
12/03/2003CN1130022C Semiconductor circuit device operating in synchronization with clock signal
12/03/2003CN1130021C Output circuit
12/03/2003CN1130020C Electrostatic protection circuit
12/03/2003CN1129969C Reference voltage semiconductor device
12/02/2003US6658656 Method and apparatus for creating alternative versions of code segments and dynamically substituting execution of the alternative code versions
12/02/2003US6658638 Power saving methods for programmable logic arrays
12/02/2003US6658637 Semiconductor device trimming method, semiconductor device trimming apparatus, and method for creating semiconductor device trimming table
12/02/2003US6657474 Circuits for a low swing clocking scheme
12/02/2003US6657470 Master/slave method for a ZQ-circuitry in multiple die devices
12/02/2003US6657468 Apparatus and method for controlling edge rates of digital signals
12/02/2003US6657467 Delay control circuit with internal power supply voltage control
12/02/2003US6657462 Conditional clock buffer circuit
12/02/2003US6657460 Spatially filtered data bus drivers and receivers and method of operating same
12/02/2003US6657459 Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them
12/02/2003US6657458 Output buffer with feedback from an input buffer to provide selectable PCL, GTL, or PECL compatibility
12/02/2003US6657457 Data transfer on reconfigurable chip
12/02/2003US6657456 Programmable logic with on-chip DLL or PLL to distribute clock
12/02/2003US6657314 Manipulation-proof integrated circuit
11/2003
11/27/2003WO2003098244A1 Cell with fixed output voltage for integrated circuit
11/27/2003US20030221151 Field programmable device
11/27/2003US20030221141 Software-based watchdog method and apparatus
11/27/2003US20030221031 Bus control device altering drive capability according to condition
11/27/2003US20030221013 Methods, systems, and devices using reprogrammable hardware for high-speed processing of streaming data to find a redefinable pattern and respond thereto
11/27/2003US20030219043 Data receiving circuit that can correctly receive data, even when high-speed data transmission is performed, using small amplitude clock
11/27/2003US20030218915 Semiconductor device adapted for power shutdown and power resumption
11/27/2003US20030218914 Semiconductor device with impedance control circuit
11/27/2003US20030218491 Master clock input circuit
11/27/2003US20030218480 Low power clock distribution scheme
11/27/2003US20030218479 Tileable field-programmable gate array architecture
11/27/2003US20030218478 Regulation of crowbar current in circuits employing footswitches/headswitches
11/27/2003US20030218477 Circuit and method for controlling on-die signal termination
11/26/2003EP1365530A1 Data receiving demultiplexer
11/26/2003EP1365513A2 General-purpose logic-cell, logic array using the same, and ASIC using this logic array
11/26/2003EP1364460A1 Interface circuit for a differential signal
11/26/2003EP0829966B1 Output circuit
11/26/2003EP0809888B1 A novel logic family employing two-terminal chalcogenide switches as the logic gates therein
11/26/2003CN2588432Y Power supply structure for more than one group power voltage used in low power consumption
11/26/2003CN1458743A Latch circuit
11/26/2003CN1129066C Processor and operational method and data processor
11/25/2003US6654944 Two-dimensional C-element array