| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 06/17/2004 | US20040113652 Apparatus and method for precisely controlling termination impedance |
| 06/17/2004 | US20040113642 Interface circuit coupling semiconductor test apparatus with tested semiconductor device |
| 06/17/2004 | US20040113224 Semiconductor integrated circuit |
| 06/17/2004 | DE202004006184U1 Gate array or field programmable gate array using logic elements which can be set for different Boolean operations |
| 06/17/2004 | DE10255642A1 Method for transmsision of digital signal, e.g. according to low voltage digital signalling (LVDS) standard, usign driver stage supplied with current via positive and negative supply |
| 06/17/2004 | DE10255626A1 Verfahren und Vorrichtung zum Anordnen von Kontaktierungselementen von Bauelementen eines integrierten Schaltkreises, Computerlesbares Speichermedium und Programm-Element Method and apparatus for disposing of contacting of components of an integrated circuit, computer readable storage medium and program element |
| 06/16/2004 | EP1429266A2 Method for composing memory on programmable platform devices to meet varied memory requirements with a fixed set of resources |
| 06/16/2004 | EP1428317A2 High voltage cmos output driver in low voltage process |
| 06/16/2004 | EP1428155A2 Structures and methods for selectively applying a well bias to portions of a programmable device |
| 06/16/2004 | CN2620945Y 1 bit CMOS full adder circuit having low voltage low power consumption and high speed |
| 06/16/2004 | CN1505267A 接收机电路 Receiver circuit |
| 06/16/2004 | CN1505265A Output signal circuit capable of automatic detection of polarity |
| 06/16/2004 | CN1505264A Multiple channel power supply control circuit |
| 06/16/2004 | CN1505151A Self-reparable semiconductor and method thereof |
| 06/15/2004 | US6751723 Field programmable gate array and microcontroller system-on-a-chip |
| 06/15/2004 | US6750697 Configuration and method for switching transistors |
| 06/15/2004 | US6750696 Level conversion circuit converting logic level of signal |
| 06/15/2004 | US6750694 Signal clipping circuit |
| 06/15/2004 | US6750684 Input circuit buffer supporting a low voltage interface and a general low voltage transistor logic(LVVTL) interface |
| 06/15/2004 | US6750681 High speed current mode logic gate circuit architecture |
| 06/15/2004 | US6750680 Semiconductor integrated circuit, logic operation circuit, and flip flop |
| 06/15/2004 | US6750679 Clocked full-rail differential logic with sense amplifier and single-rail logic |
| 06/15/2004 | US6750678 Method for increasing the load capacity of clocked half-rail differential logic |
| 06/15/2004 | US6750677 Dynamic semiconductor integrated circuit |
| 06/15/2004 | US6750676 Driving circuit |
| 06/15/2004 | US6750675 Programmable logic devices with multi-standard byte synchronization and channel alignment for communication |
| 06/15/2004 | US6750674 Carry chain for use between logic modules in a field programmable gate array |
| 06/10/2004 | WO2004049572A1 Seu hard majority voter for triple redundancy |
| 06/10/2004 | WO2002095942A3 Dual-edge triggered dynamic logic |
| 06/10/2004 | US20040111691 Mask-programmable logic device with building block architecture |
| 06/10/2004 | US20040111690 Method for composing memory on programmable platform devices to meet varied memory requirements with a fixed set of resources |
| 06/10/2004 | US20040111684 Design method of logic circuit |
| 06/10/2004 | US20040108889 Semiconductor integrated circuit |
| 06/10/2004 | US20040108886 Emulation of long delay chain by ring oscillator with floating body-tied body devices |
| 06/10/2004 | US20040108885 Interface circuit |
| 06/10/2004 | US20040108884 Semiconductor integrated circuit with sleep memory |
| 06/10/2004 | US20040108873 Pseudofooter circuit for dynamic CMOS (Complementary metal-oxide-semiconductor) logic |
| 06/10/2004 | US20040108872 Voltage-controlled delay line with reduced timing errors and jitters |
| 06/10/2004 | US20040108871 Use of dangling partial lines for interfacing in a PLD |
| 06/09/2004 | EP1425902A2 Multi-standard channel decoder for real-time digital broadcast reception |
| 06/09/2004 | EP1425650A2 Method for smoothing di/dt noise due to clock transitions |
| 06/09/2004 | CN1503452A 半导体装置及其驱动方法 Semiconductor device and method of driving |
| 06/09/2004 | CN1503440A Voltage step down circuit, power source circuit ands emiconductor integrated circuit |
| 06/09/2004 | CN1153349C Multiple-valued logic circuit arthitecture. supplementary symmetrical logic circuit structure (SUS-LOG) |
| 06/09/2004 | CN1153270C Method and device for eliminating parasitic bipolar transistor effect |
| 06/09/2004 | CN1153111C Manipulation proof integrated circuit |
| 06/08/2004 | US6748577 System for simplifying the programmable memory to logic interface in FPGA |
| 06/08/2004 | US6748456 PLD configuration port architecture and logic |
| 06/08/2004 | US6748368 Proprietary core permission structure and method |
| 06/08/2004 | US6747903 Configurable decoder for addressing a memory |
| 06/08/2004 | US6747504 Controlled rise time output driver |
| 06/08/2004 | US6747483 Differential memory interface system |
| 06/08/2004 | US6747482 Architecture and interconnect scheme for programmable logic circuits |
| 06/08/2004 | US6747481 Adaptive algorithm for electrical fuse programming |
| 06/08/2004 | US6747480 Programmable logic devices with bidirect ional cascades |
| 06/08/2004 | US6747479 Interface scheme for connecting a fixed circuitry block to a programmable logic core |
| 06/08/2004 | US6747478 Field programmable gate array with convertibility to application specific integrated circuit |
| 06/08/2004 | US6747474 Integrated circuit stubs in a point-to-point system |
| 06/03/2004 | WO2004047297A1 Level shifting circuit between isolated systems |
| 06/03/2004 | WO2004047269A2 Flip-flop circuit |
| 06/03/2004 | WO2004027777A3 A fast controlled output buffer |
| 06/03/2004 | WO2004015596A3 Method and system for debugging using replicated logic |
| 06/03/2004 | WO2003025763A3 Functional pathway configuration at a system/ic interface |
| 06/03/2004 | US20040107383 Service processor with algorithms for supporting a multi partition computer |
| 06/03/2004 | US20040107303 Configurable integrated circuit for use in a multi-function handheld device |
| 06/03/2004 | US20040107060 Output circuit and method for reducing simultaneous switching output skew |
| 06/03/2004 | US20040105918 a power control circuit that can manage and control both the active and standby modes of each circuit block of a chip |
| 06/03/2004 | US20040105517 Receiver circuit |
| 06/03/2004 | US20040105317 Slew rate controlling method and system for output data |
| 06/03/2004 | US20040104762 Bias potential generating apparatus |
| 06/03/2004 | US20040104760 Complementary source follower circuit controlled by back bias voltage |
| 06/03/2004 | US20040104757 System and method to establish an adjustable on-chip impedance |
| 06/03/2004 | US20040104748 Input circuit, display device and information display apparatus |
| 06/03/2004 | US20040104745 Hold time latch with decreased precharge node voltage leakage |
| 06/03/2004 | US20040104744 Dynamic logic circuits using transistors having differing threshold voltages and delayed low threshold voltage leakage protection |
| 06/03/2004 | US20040104743 Driving circuit |
| 06/02/2004 | EP1424775A1 Dynamic logic circuits using transistors having differing threshold voltages and delayed low threshold voltage leakage protection |
| 06/02/2004 | EP1424733A2 Method and device for arranging contacts of elements on an integrated circuit, computer readable memory device, and program element |
| 06/02/2004 | EP1424619A2 Master slice semiconductor integrated circuit |
| 06/02/2004 | EP1423951A1 Differential line driver with on-chip termination |
| 06/02/2004 | EP1423789A2 Data processing system having an on-chip background debug system and method therefor |
| 06/02/2004 | EP1423785A2 Power raising circuit |
| 06/02/2004 | EP1002319B1 A ferroelectric data processing device |
| 06/02/2004 | CN1152435C Method and device for reducing parasitic bipolar current of silicon transistor on insulator |
| 06/01/2004 | US6745357 Dynamic logic scan gate method and apparatus |
| 06/01/2004 | US6744300 Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation |
| 06/01/2004 | US6744298 Semiconductor device |
| 06/01/2004 | US6744297 Inverter circuit |
| 06/01/2004 | US6744294 Cascode signal driver with low harmonic content |
| 06/01/2004 | US6744288 Driver with bulk switching MOS power transistor |
| 06/01/2004 | US6744283 Clocked half-rail differential logic with sense amplifier |
| 06/01/2004 | US6744282 Latching dynamic logic structure, and integrated circuit including same |
| 06/01/2004 | US6744280 Voltage output differential (VOD) correction circuit for differential drivers |
| 06/01/2004 | US6744278 Tileable field-programmable gate array architecture |
| 06/01/2004 | US6744274 Programmable logic core adapter |
| 05/27/2004 | WO2004044952A2 Integrated circuit with automatic pin-strapping configuration |
| 05/27/2004 | US20040103382 Master slice semiconductor integrated circuit |
| 05/27/2004 | US20040100838 Buffer circuit device supplying a common mode voltage applicable to a next-stage circuit receiving output signals of the buffer circuit device |
| 05/27/2004 | US20040100318 Level shifter and latch with the same built in |
| 05/27/2004 | US20040100309 Method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time |