| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 07/06/2004 | US6759701 Transistor circuit |
| 07/01/2004 | WO2004055987A1 Semiconductor device and display apparatus using the same |
| 07/01/2004 | WO2004055986A2 Reconfiguration of the programmable logic of an integrated circuit |
| 07/01/2004 | WO2004055985A1 Method and device for charge recovery in an integrated circuit |
| 07/01/2004 | WO2004032199A3 Constant delay zero standby differential logic receiver and method |
| 07/01/2004 | WO2003025784A3 Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations |
| 07/01/2004 | WO2003003582B1 Low power operation mechanism and method |
| 07/01/2004 | US20040127998 Arrangement of configurable logic blocks |
| 07/01/2004 | US20040125661 Temperature-compensated output buffer circuit |
| 07/01/2004 | US20040125660 Nonvolatile memory device efficiently changing functions of field programmable gate array at high speed |
| 07/01/2004 | US20040125102 Display device |
| 07/01/2004 | US20040124918 Wideband common-mode regulation circuit |
| 07/01/2004 | US20040124905 Circuit configuration for signal balancing in antiphase bus drivers |
| 07/01/2004 | US20040124902 Resistance calibration circuit in semiconductor device |
| 07/01/2004 | US20040124901 Level shift circuit |
| 07/01/2004 | US20040124898 Integrated circuit |
| 07/01/2004 | US20040124890 Driver circuit |
| 07/01/2004 | US20040124882 Single stage pulsed domino circuit for driving cascaded skewed static logic circuits |
| 07/01/2004 | US20040124877 Integrated circuit and related improvements |
| 07/01/2004 | US20040124876 Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array |
| 07/01/2004 | US20040124875 Setting multiple chip parameters using one IC terminal |
| 06/30/2004 | EP1434348A1 Wideband common-mode regulation circuit |
| 06/30/2004 | EP1434238A2 Integrated circuit with programmable fuse array |
| 06/30/2004 | EP1434134A2 Self-reparable semiconductor and method thereof |
| 06/30/2004 | EP1433257A2 A reconfigurable integrated circuit with a scalable architecture |
| 06/30/2004 | CN1509431A Method and apparatus for controlling current demand in ingegrated circuit |
| 06/30/2004 | CN1508971A Static selection circuit with high reliability and cow-power consumption |
| 06/30/2004 | CN1508642A Power source supply structure more than one group of power voltage for low power consumption applications |
| 06/30/2004 | CN1508556A Coupling semiconductor testing device and interface circuit of the semiconductor device to be tested |
| 06/29/2004 | US6757872 Command user interface with programmable decoder |
| 06/29/2004 | US6756835 Level shifting circuit |
| 06/29/2004 | US6756826 Method of reducing the propagation delay and process and temperature effects on a buffer |
| 06/29/2004 | US6756824 Self-biased driver amplifiers for high-speed signaling interfaces |
| 06/29/2004 | US6756821 High speed differential signaling logic gate and applications thereof |
| 06/29/2004 | US6756818 Voltage-controlled delay line with reduced timing errors and jitters |
| 06/29/2004 | US6756816 Semiconductor device |
| 06/29/2004 | US6756815 Input buffer with selectable operational characteristics |
| 06/29/2004 | US6756814 Logic circuit and semiconductor device |
| 06/29/2004 | US6756813 Voltage translator |
| 06/29/2004 | US6756812 Differential termination resistor adjusting circuit |
| 06/29/2004 | US6756811 Customizable and programmable cell array |
| 06/29/2004 | US6756810 Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting |
| 06/29/2004 | US6756809 Single event upset immune logic family |
| 06/29/2004 | CA2359048C A regionally time multiplexed emulation system |
| 06/29/2004 | CA2170764C High speed differential receiver for data communications |
| 06/24/2004 | WO2004054106A1 High speed transmission circuit |
| 06/24/2004 | WO2004053990A1 Emulsation of long delay chain by ring oscillator with floating body-tied body transistors |
| 06/24/2004 | WO2004027545A3 High speed zero dc power programmable logic device (pld) architecture |
| 06/24/2004 | WO2003017490A8 Method and apparatus for reducing a magnitude of a rate of current change of an integrated circuit |
| 06/24/2004 | US20040120444 Instantaneous clock recovery circuit |
| 06/24/2004 | US20040120191 Semiconductor circuit comparing two data rows |
| 06/24/2004 | US20040119553 Center-tap termination circuit and printed circuit board having the same |
| 06/24/2004 | US20040119529 Powergate control using boosted and negative voltages |
| 06/24/2004 | US20040119526 I/o circuit using low voltage transistors which can tolerate high voltages even when power supplies are powered off |
| 06/24/2004 | US20040119511 Impedance controlled output driver |
| 06/24/2004 | US20040119510 Bus driver |
| 06/24/2004 | US20040119504 AC powered logic circuitry |
| 06/24/2004 | US20040119503 Gate-clocked domino circuits with reduced leakage current |
| 06/24/2004 | US20040119499 Reducing swing line driver |
| 06/24/2004 | US20040119498 Converter from ECL to CMOS and network element for transmitting signals |
| 06/24/2004 | US20040119497 Programmable I/O buffer |
| 06/24/2004 | US20040119496 Implementation of multiple flip flops as a standard cell using novel clock generation scheme |
| 06/24/2004 | US20040119494 Programmable power adjust for microelectronic devices |
| 06/24/2004 | US20040119114 a n-channel (field effective transistor)FET that operates essentially like a p-channel FET, and thus can be used as an effective replacement for the latter |
| 06/24/2004 | DE69433468T2 Logischer Schaltkreis mit Fehlernachweisfunktion A logical circuit with error detection function |
| 06/24/2004 | DE19630515B4 Interfaceschaltung zur Realisierung einer S/T-Schnittstelle nach Spezifikation ITU I.430 Interface circuit for realizing an S / T interface to specification ITU I.430 |
| 06/24/2004 | DE10255768B3 Configurable logic block device using field programmable gate array technology and incorporating look-up tables |
| 06/24/2004 | DE10144397B4 1 aus n-Decoder 1 from n decoder |
| 06/23/2004 | EP1432169A1 Instantaneous clock recovery circuit |
| 06/23/2004 | EP1432126A2 High performance interconnect architecture for FPGAs |
| 06/23/2004 | EP1432125A1 ECL-CMOS converter for a digital network |
| 06/23/2004 | EP1430673A2 Apparatus and method for power efficient line driver |
| 06/23/2004 | CN1507285A Method of realizing router chip of group exchange network with FPGA device |
| 06/23/2004 | CN1507155A Digital potential converter and integrated circuit thereof |
| 06/23/2004 | CN1507049A Semiconductor integrated circuit equipment and method for detecting delay error in the same equipment |
| 06/23/2004 | CN1507048A Method and circuit for reducing leakage of grid under the state of dormancy |
| 06/22/2004 | US6753708 Driver circuit connected to pulse shaping circuitry and method of operating same |
| 06/22/2004 | US6753702 Semiconductor integrated circuit and its layout method |
| 06/22/2004 | US6753700 Universal single-ended parallel bus |
| 06/22/2004 | US6753699 Integrated circuit and method of controlling output impedance |
| 06/22/2004 | US6753698 Low power low voltage transistor—transistor logic I/O driver |
| 06/22/2004 | US6753697 Semiconductor device capable of maintaining output signal even if internal power supply potential is turned off |
| 06/22/2004 | US6753696 Programmable optimized-distribution logic allocator for a high-density complex PLD |
| 06/22/2004 | US6753694 Single event upset immune logic family |
| 06/17/2004 | WO2004051853A2 Magnetic logic device |
| 06/17/2004 | WO2004038554A3 System with multiple path fail over, fail back and load balancing |
| 06/17/2004 | WO2004027995A3 Integrated circuit comprising an sstl (stub series terminated logic) pre-driver stage using regulated power supply and method for performing an sstl operation |
| 06/17/2004 | WO2003030009A3 Programmable gate array having interconnecting logic to support embedded fixed logic circuitry |
| 06/17/2004 | WO2002082651A3 Circuit for performing a digital logic operation |
| 06/17/2004 | US20040117755 Reconfiguration of a programmable logic device using internal control |
| 06/17/2004 | US20040117754 Power saving methods for programmable logic arrays |
| 06/17/2004 | US20040117553 Memory card |
| 06/17/2004 | US20040113676 Input buffer |
| 06/17/2004 | US20040113672 Low-power high-performance integrated circuit and related methods |
| 06/17/2004 | US20040113670 Semiconductor integrated circuit device and method of detecting delay error in the same |
| 06/17/2004 | US20040113664 Data output buffer having a preset structure |
| 06/17/2004 | US20040113657 Technique for mitigating gate leakage during a sleep state |
| 06/17/2004 | US20040113656 Differential data transmitter |
| 06/17/2004 | US20040113654 Apparatus and method for adjusting the impedance of an output driver |
| 06/17/2004 | US20040113653 Output driver impedance controller |