Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
12/2005
12/22/2005WO2005122405A1 Repeater circuit with high performance and normal repeater modes
12/22/2005WO2005122404A1 Repeater circuit with high performance and normal repeater modes and reset capability
12/22/2005WO2005122403A1 Repeater circuit having different operating and reset voltage ranges, and methods thereof
12/22/2005WO2005122402A1 Circuits and methods for detecting and assisting wire transitions
12/22/2005WO2005112263A3 Low swing current mode logic family
12/22/2005US20050283749 Dynamic slew rate controlling method and device for reducing variance in simultaneous switching output
12/22/2005US20050280451 Low-consumption inhibit circuit with hysteresis
12/22/2005US20050280445 Pseudo CMOS dynamic logic with delayed clocks
12/22/2005US20050280443 Power-aware configurable driver circuits for lines terminated by a load
12/22/2005US20050280442 Semiconductor integrated circuit
12/22/2005US20050280441 Integrated circuit
12/22/2005US20050280440 Predriver circuit
12/22/2005US20050280438 Switch methodology for mask-programmable logic devices
12/22/2005US20050280437 Apparatus and methods for adjusting performance of integrated circuits
12/22/2005US20050280436 Nanotube-based logic driver circuits
12/22/2005US20050280435 Output buffer with time varying source impedance for driving capacitively-terminated transmission lines
12/22/2005US20050280083 Standby current reduction over a process window with a trimmable well bias
12/22/2005US20050280058 Re-configurable logic elements using heat assisted magnetic tunneling elements
12/22/2005DE4426841B4 Signalübertragungseinrichtung Signal transmission device
12/22/2005DE19959405B4 Umkonfigurierbare Geräteschnittstelle Reconfigurable device interface
12/22/2005DE102005022684A1 Decision feedback equalization input buffer for memory device, has equalizing controller that modifies variable equalizing control signal in response to timing control signal generated by phase detector
12/22/2005DE102004025581A1 Logik-Grundzelle und Logik-Grundzellen-Anordnung Logic basic cell and logic basic cell arrangement
12/21/2005EP1608119A2 System and method for actively terminating a transmission line
12/21/2005EP1608071A1 Reconfigurable logical circuit using transistor having spin-dependent transmission characteristic
12/21/2005EP1608070A2 Multi-bit digital input using a single pin
12/21/2005EP1608069A2 Method for controling an analog switch
12/21/2005EP1607887A2 Power-aware configurable driver circuits for lines terminated by a load
12/21/2005EP1606892A2 Low noise hybrid circuit for communications systems using time division multiplexing
12/21/2005EP1606879A1 Magnetic logic device and method for the operation thereof
12/21/2005EP1606878A1 Electronic circuit with array of programmable logic cells
12/21/2005EP1257928B1 Reconfigurable logic for a computer
12/21/2005EP1201033B1 Circuit configuration for supplying power to an integrated circuit via a pad
12/21/2005CN1711690A Level shifting circuit between isolated systems
12/21/2005CN1711687A Turn-on bus transmitter with controlled slew rate
12/21/2005CN1233094C Non-complementary CMOS AND-NOT circuit structure
12/20/2005US6978434 Method of designing wiring structure of semiconductor device and wiring structure designed accordingly
12/20/2005US6978387 Hold time latch with decreased percharge node voltage leakage
12/20/2005US6978333 Method and system for reducing aggregate impedance discontinuity between expansion connectors
12/20/2005US6977528 Event driven dynamic logic for reducing power consumption
12/20/2005US6977527 Method and apparatus for suppressing spurious values in a differential output current
12/20/2005US6977526 Fully differential input buffer with wide signal swing range
12/20/2005US6977525 Current driver circuit
12/20/2005US6977524 High current 5V tolerant buffer using a 2.5 volt power supply
12/20/2005US6977523 Voltage level shifting circuit
12/20/2005US6977522 Interface device and information processing system
12/20/2005US6977521 Field programmable gate array
12/20/2005US6977520 Time-multiplexed routing in a programmable logic device architecture
12/20/2005US6977519 Digital logic with reduced leakage
12/15/2005WO2005119916A1 Low voltage high-speed differential logic devices and method of use thereof
12/15/2005WO2005119915A2 Current mode logic buffer
12/15/2005WO2005119914A1 Headswitch and footswitch circuitry for power management
12/15/2005WO2005119913A2 Schottky device
12/15/2005WO2005119912A1 Coil load drive output circuit
12/15/2005WO2005119532A2 Low-power fpga circuits and methods
12/15/2005WO2005119471A2 Bus controller
12/15/2005WO2005034175A3 Programmable system on a chip
12/15/2005US20050278677 Novel test structure for automatic dynamic negative-bias temperature instability testing
12/15/2005US20050278675 General purpose delay logic
12/15/2005US20050278672 LSI design method
12/15/2005US20050277240 Logic components from organic field effect transistors
12/15/2005US20050276132 Headswitch and footswitch circuitry for power management
12/15/2005US20050276126 Programmable impedance control circuit in semiconductor device and impedance range shifting method thereof
12/15/2005US20050275448 Control method for an analogue switch
12/15/2005US20050275442 Signal generator circuit and level shifter with signal generator circuit
12/15/2005US20050275440 Technique for operating a delay circuit
12/15/2005US20050275435 Comparator using differential amplifier with reduced current consumption
12/15/2005US20050275432 High voltage tolerant off chip driver circuit
12/15/2005US20050275431 High-speed low-voltage differential signaling buffer using a level shifter
12/15/2005US20050275430 Voltage level shifting circuit and method
12/15/2005US20050275429 Single supply level shifter
12/15/2005US20050275428 Field programmable gate array logic unit and its cluster
12/15/2005US20050275427 Field programmable gate array logic unit and its cluster
12/15/2005US20050275426 Multiple-time programming apparatus and method using one-time programming element
12/15/2005US20050275425 Memory system with a scheme capable of stably terminating a pair of differential signals transmitted via a pair of transmission lines
12/15/2005US20050275424 Reducing electrical noise during bus turnaround in signal transfer systems
12/15/2005US20050275055 Schottky device
12/15/2005DE19600049B4 Selbstbootstrapvorrichtung Selbstbootstrapvorrichtung
12/14/2005CN1708903A System for reducing leakage in integrated circuits
12/14/2005CN1708897A Differential circuit and receiver with same
12/14/2005CN1707953A Semiconductor device
12/14/2005CN1707952A Electronic system, semiconductor integrated circuit and terminal apparatus
12/14/2005CN1707949A Semiconductor integrated circuit
12/14/2005CN1707773A Standard cell, semiconductor integrated circuit device of standard cell scheme and layout design method for semiconductor integrated circuit device
12/14/2005CN1232041C Reconfigurable logic device and multiplying array including the same device
12/14/2005CN1232040C Semiconductor integrated circuit
12/14/2005CN1232039C Semiconductor integrated circuit
12/14/2005CN1232038C Output buffer capable of reducing power source and earthing pop-corn noise and its method
12/14/2005CN1232037C Circuit capable of generating control signal in linear current and method thereof
12/14/2005CN1232032C Level transforming circuit for transforming signal logistic level
12/13/2005US6976160 Method and system for controlling default values of flip-flops in PGA/ASIC-based designs
12/13/2005US6976118 Method and system for programming FPGAs on PC-cards without additional hardware
12/13/2005US6975533 Hybrid semiconductor—magnetic spin based memory with low transmission barrier
12/13/2005US6975489 Circuit structure and semiconductor integrated circuit
12/13/2005US6975160 System including an integrated circuit memory device having an adjustable output voltage setting
12/13/2005US6975159 Method of operation in a system having a memory device having an adjustable output voltage setting
12/13/2005US6975155 Level shifting circuit and method
12/13/2005US6975147 Data output circuit with reduced output noise
12/13/2005US6975143 Static logic design for CMOS
12/13/2005US6975142 Semiconductor device
12/13/2005US6975141 LVDS driver for small supply voltages
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