Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
10/2010
10/05/2010US7807999 Array substrate, liquid crystal display apparatus having the same and method for driving liquid crystal display apparatus
10/05/2010US7807995 Nonvolatile semiconductor memory apparatus and manufacturing method thereof
10/05/2010US7807989 Phase-change memory using single element semimetallic layer
10/05/2010US7807546 SRAM cell having stepped boundary regions and methods of fabrication
10/05/2010US7807534 Method for manufacturing semiconductor device and semiconductor device manufactured therefrom
10/05/2010US7807530 Semiconductor integrated circuit device and a method of manufacturing the same
10/05/2010US7807520 Method for manufacturing semiconductor device
10/05/2010US7807518 Semiconductor memory device and manufacturing method thereof
10/05/2010US7807500 Process for production of SOI substrate and process for production of semiconductor device including the selective forming of porous layer
10/05/2010CA2548932C Apparatus and methods for resizing electronic displays
09/2010
09/30/2010WO2010111286A2 High temperature thin film transistor on soda lime glass
09/30/2010WO2010111083A2 Structure and method for forming a salicide on the gate electrode of a trench-gate fet
09/30/2010WO2010110928A1 Methods of forming semiconductor devices including epitaxial layers and related structures
09/30/2010WO2010110904A1 Structure and fabrication of field-effect transistor using empty well in combination with source/drain extensions or/and halo pocket
09/30/2010WO2010110903A1 Structure and fabrication of field-effect transistor having nitrided gate dielectric layer with tailored vertical nitrogen concentration profile
09/30/2010WO2010110902A1 Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses
09/30/2010WO2010110901A1 Fabrication and structure of asymmetric field-effect transistors using l-shaped spacers
09/30/2010WO2010110900A1 Structure and fabrication of field-effect transistor having source/drain extension defined by multiple local concentration maxima
09/30/2010WO2010110895A1 Configuration and fabrication of semiconductor structure in which source and drain extensions of field-effect transistor are defined with different dopants
09/30/2010WO2010110894A1 Structure and fabrication of asymmetric field-effect transistor having asymmetric channel zone and differently configured source/drain extensions
09/30/2010WO2010110893A1 Configuration and fabrication of semiconductor structure using empty and filled wells
09/30/2010WO2010110891A1 Configuration and fabrication of semiconductor structure having bipolar junction transistor in which non-monocrystalline semiconductor spacing portion controls base-link length
09/30/2010WO2010110890A1 Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone
09/30/2010WO2010110803A1 Switchable junction with intrinsic diode
09/30/2010WO2010110733A1 A schottky device
09/30/2010WO2010110725A1 Silicon carbide bipolar junction transistor
09/30/2010WO2010110571A2 Oxide semiconductor and thin film transistor including the same
09/30/2010WO2010110475A1 Shot key-type junction element and photoelectric conversion element and solar cell using the same
09/30/2010WO2010110351A1 Tetrathiafulvalene derivative, and organic film and organic transistor using the same
09/30/2010WO2010110297A1 Magnetic sensor and magnetic-storage device
09/30/2010WO2010110294A1 Substrate fixing structure and physical quantity sensor
09/30/2010WO2010110253A1 Mosfet and method for manufacturing mosfet
09/30/2010WO2010110252A1 Mosfet and method for manufacturing mosfet
09/30/2010WO2010110246A1 Semiconductor device
09/30/2010WO2010110180A1 Semiconductor device and method for manufacturing same
09/30/2010WO2010110179A1 Active element substrate and manufacturing method thereof, and display apparatus using active element substrate manufactured by this manufacturing method
09/30/2010WO2010109963A1 Nonvolatile programmable logic switch
09/30/2010WO2010109892A1 Semiconductor substrate, semiconductor device, and method of producing semiconductor substrate
09/30/2010WO2010109712A1 Insulating substrate for semiconductor device, and semiconductor device
09/30/2010WO2010109596A1 Semiconductor device
09/30/2010WO2010109572A1 Semiconductor device
09/30/2010WO2010109566A1 Semiconductor device and method for manufacturing same
09/30/2010WO2010108978A1 Rectifier diode
09/30/2010WO2010080296A3 Lateral mosfet with substrate drain connection
09/30/2010WO2010078204A3 Quantum well mosfet channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains
09/30/2010WO2010068055A3 Planar gate-controlled element and method for fabricating the same
09/30/2010WO2009102520A9 Microcrystalline silicon thin film transistor
09/30/2010US20100248676 Semiconductor device
09/30/2010US20100248402 Semiconductor device and manufacturing method thereof, delamination method, and transferring method
09/30/2010US20100248209 Three-dimensional integrated circuit for analyte detection
09/30/2010US20100246263 Non-volatile Memory Device
09/30/2010US20100246257 Fabricating and operating a memory array having a multi-level cell region and a single-level cell region
09/30/2010US20100246252 Nonvolatile solid state magnetic memory and recording method thereof
09/30/2010US20100246245 Spin-torque memory with unidirectional write scheme
09/30/2010US20100246079 Power supply clamp circuit
09/30/2010US20100245970 Light control device, semiconductor wafer, and light control system
09/30/2010US20100245969 Coupled quantum well structure
09/30/2010US20100245302 Display device
09/30/2010US20100244965 Semiconductor device and its manufacture method
09/30/2010US20100244934 Soi radio frequency switch with enhanced electrical isolation
09/30/2010US20100244897 Spin mosfet and reconfigurable logic circuit
09/30/2010US20100244248 Nonvolatile memory device and method for manufacturing same
09/30/2010US20100244203 Semiconductor structure having a protective layer
09/30/2010US20100244198 Cmos sige channel pfet and si channel nfet devices with minimal sti recess
09/30/2010US20100244197 Epitaxial methods and structures for reducing surface dislocation density in semiconductor materials
09/30/2010US20100244196 Group III nitride semiconductor composite substrate, group III nitride semiconductor substrate, and group III nitride semiconductor composite substrate manufacturing method
09/30/2010US20100244195 Host substrate for nitride based light emitting devices
09/30/2010US20100244194 Semiconductor device and manufacturing method thereof
09/30/2010US20100244193 System-in-Package Having Integrated Passive Devices and Method Therefor
09/30/2010US20100244192 Dielectric film and semiconductor device using dielectric film
09/30/2010US20100244191 Semiconductor device
09/30/2010US20100244190 Semiconductor device and manufacturing method
09/30/2010US20100244189 Integration substrate with a ultra-high-density capacitor and a through-substrate via
09/30/2010US20100244188 Semiconductor device and manufacturing method thereof
09/30/2010US20100244187 Esd network circuit with a through wafer via structure and a method of manufacture
09/30/2010US20100244184 Method of Forming an Electrical Contact Between a Support Wafer and the Surface of a Top Silicon Layer of a Silicon-on-Insulator Wafer and an Electrical Device Including Such an Electrical Contact
09/30/2010US20100244183 Integrated semiconductor device and method of manufacturing the same
09/30/2010US20100244182 Method of manufacturing laminated wafer by high temperature laminating method
09/30/2010US20100244181 Filling Gaps in Integrated Circuit Fabrication
09/30/2010US20100244180 Method for fabricating device isolation structure
09/30/2010US20100244179 Structure and method for latchup improvement using through wafer via latchup guard ring
09/30/2010US20100244178 Field effect transistor gate process and structure
09/30/2010US20100244162 Mems device with reduced stress in the membrane and manufacturing method
09/30/2010US20100244161 Wafer level packaging using flip chip mounting
09/30/2010US20100244160 Mems sensor, mems sensor manufacturing method, and electronic device
09/30/2010US20100244159 Eutectic flow containment in a semiconductor fabrication process
09/30/2010US20100244158 Semiconductor structures resulting from selective oxidation
09/30/2010US20100244157 Semiconductor device
09/30/2010US20100244156 Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods
09/30/2010US20100244155 Maintaining integrity of a high-k gate stack by an offset spacer used to determine an offset of a strain-inducing semiconductor alloy
09/30/2010US20100244154 Semiconductor device including misfet
09/30/2010US20100244153 Method of fabricating spacers in a strained semiconductor device
09/30/2010US20100244152 Configuration and fabrication of semiconductor structure having extended-drain field-effect transistor
09/30/2010US20100244151 Structure and fabrication of field-effect transistor having source/drain extension defined by multiple local concentration maxima
09/30/2010US20100244150 Configuration and fabrication of semiconductor structure in which source and drain extensions of field-effect transistor are defined with different dopants
09/30/2010US20100244149 Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses
09/30/2010US20100244148 Structure and fabrication of field-effect transistor having nitrided gate dielectric layer with tailored vertical nitrogen concentration profile
09/30/2010US20100244147 Configuration and fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portions along source/drain zone
09/30/2010US20100244139 Strained-silicon cmos device and method
09/30/2010US20100244138 Semiconductor varactor with reduced parasitic resistance
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