Patents
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
04/2014
04/17/2014US20140103459 Semiconductor device and method for fabricating the same
04/17/2014US20140103458 Gate electrode having a capping layer
04/17/2014US20140103457 Field effect transistor device having a hybrid metal gate stack
04/17/2014US20140103456 Field effect transistor with narrow bandgap source and drain regions and method of fabrication
04/17/2014US20140103455 FET Devices with Oxide Spacers
04/17/2014US20140103454 Lightly Doped Source/Drain Last Method For Dual-EPI Integration
04/17/2014US20140103453 Control Fin Heights in FinFET Structures
04/17/2014US20140103452 Isolation components for transistors formed on fin features of semiconductor substrates
04/17/2014US20140103449 Oxygen free rta on gate first hkmg stacks
04/17/2014US20140103444 Semiconductor device with a dislocation structure and method of forming the same
04/17/2014US20140103443 Semiconductor device having metal gate and manufacturing method thereof
04/17/2014US20140103442 Semiconductor device, method of forming semiconductor device, and data processing system
04/17/2014US20140103441 Semiconductor device and method of fabricating the same
04/17/2014US20140103440 I-shaped gate electrode for improved sub-threshold mosfet performance
04/17/2014US20140103439 Transistor Device and Method for Producing a Transistor Device
04/17/2014US20140103438 Multi-gate semiconductor devices and methods of forming the same
04/17/2014US20140103437 Random Doping Fluctuation Resistant FinFET
04/17/2014US20140103435 Vertical source/drain junctions for a finfet including a plurality of fins
04/17/2014US20140103434 Multi-finger transistor layout for reducing cross-finger electric variations and for fully utilizing available breakdown voltages
04/17/2014US20140103433 High-voltage metal-dielectric-semiconductor device and method of the same
04/17/2014US20140103432 Semiconductor device
04/17/2014US20140103431 Laterally double diffused metal oxide semiconductor transistors having a reduced surface field structures
04/17/2014US20140103430 Lateral high-voltage transistor and method for manufacturing the same
04/17/2014US20140103429 Method and Structure to Boost MOSFET Performance and NBTI
04/17/2014US20140103428 Trench superjunction mosfet with thin epi process
04/17/2014US20140103427 Semiconductor transistor device and method for manufacturing same
04/17/2014US20140103426 Trench metal oxide semiconductor field effect transistor with multiple trenched source-body contacts for reducing gate charge
04/17/2014US20140103425 Semiconductor device
04/17/2014US20140103424 Electronic device comprising conductive structures and an insulating layer between the conductive structures and within a trench
04/17/2014US20140103423 Method of producing precision vertical and horizontal layers in a vertical semiconductor structure
04/17/2014US20140103422 Structure for mems transistors on far back end of line
04/17/2014US20140103421 Semiconductor devices and method of making the same
04/17/2014US20140103420 Advanced faraday shield for a semiconductor device
04/17/2014US20140103418 Sonos type stacks for nonvolatile changetrap memory devices and methods to form the same
04/17/2014US20140103417 Semiconductor device and method of manufacturing the same
04/17/2014US20140103416 Semiconductor device having esd protection structure and associated method for manufacturing
04/17/2014US20140103409 Soi substrate and manufacturing method thereof
04/17/2014US20140103407 Method For Protecting a Gate Structure During Contact Formation
04/17/2014US20140103406 Semiconductor structure with reduced junction leakage and method of fabrication thereof
04/17/2014US20140103405 Method for fabricating semiconductor device
04/17/2014US20140103404 Replacement gate with an inner dielectric spacer
04/17/2014US20140103403 Method for manufacturing semiconductor device
04/17/2014US20140103402 Semiconductor Structure Having Contact Plug and Metal Gate Transistor and Method of Making the Same
04/17/2014US20140103399 Gallium nitride power devices
04/17/2014US20140103398 Rf power hemt grown on a silicon or sic substrate with a front-side plug connection
04/17/2014US20140103397 Techniques for forming non-planar germanium quantum well devices
04/17/2014US20140103396 Strain-inducing semiconductor regions
04/17/2014US20140103395 Semiconductor element
04/17/2014US20140103394 Reduction of Edge Effects from Aspect Ratio Trapping
04/17/2014US20140103393 Surface Mountable Power Components
04/17/2014US20140103366 Silicon device on si:c-oi and sgoi and method of manufacture
04/17/2014US20140103365 Semiconductor device and method for manufacturing same
04/17/2014US20140103364 Switching device
04/17/2014US20140103363 Using stress reduction barrier sub-layers in a semiconductor die
04/17/2014US20140103360 Semiconductor device
04/17/2014US20140103358 Composite Substrate
04/17/2014US20140103357 Schottky diode structure and method of fabrication
04/17/2014US20140103354 Nitride semiconductor structure
04/17/2014US20140103353 Group iii nitride composite substrate and method for manufacturing the same, laminated group iii nitride composite substrate, and group iii nitride semiconductor device and method for manufacturing the same
04/17/2014US20140103352 Nitride semiconductor and fabricating method thereof
04/17/2014US20140103351 Low Temperature Poly-Silicon Thin Film Transistor, Manufacturing Method thereof, and Display Device
04/17/2014US20140103349 Different lightly doped drain length control for self-align light drain doping process
04/17/2014US20140103346 Semiconductor device
04/17/2014US20140103345 Thin film transistor and method for manufacturing the same, array substrate, and display device
04/17/2014US20140103343 Pixel drive circuit and preparation method therefor, and array substrate
04/17/2014US20140103342 Tft substrate and method for manufacturing same
04/17/2014US20140103341 Method for producing amorphous oxide thin film and thin film transistor
04/17/2014US20140103340 Semiconductor device
04/17/2014US20140103339 Semiconductor device and method for manufacturing the same
04/17/2014US20140103338 Semiconductor device
04/17/2014US20140103337 Semiconductor device
04/17/2014US20140103335 Semiconductor device
04/17/2014US20140103334 Oxide Semiconductor Thin Film Transistor, Manufacturing Method, And Display Device Thereof
04/17/2014US20140103332 Thin film transistor display panel
04/17/2014US20140103331 Embedded Source/Drains with Epitaxial Oxide Underlayer
04/17/2014US20140103317 Thin film transistor array panel and organic light emitting diode display including the same
04/17/2014US20140103307 Vertical thin-film transistor structure of display panel and method of fabricating the same
04/17/2014US20140103299 Nanotube array electronic and opto-electronic devices
04/17/2014US20140103297 Organic material-based graphitic material
04/17/2014US20140103294 Techniques and configurations to impart strain to integrated circuit devices
04/17/2014US20140103268 In2o3-sno2-zno sputtering target
04/17/2014DE112012003231T5 CMOS-Transistor mit epitaxialer Erweiterung CMOS transistor with epitaxial expansion
04/17/2014DE112012001617T5 Siliziumkarbid-Vertikalfeldeffekttransistor Silicon carbide vertical field effect transistor
04/17/2014DE102013215378A1 Lateraler Hochspannungstransistor und Verfahren zu seiner Herstellung A lateral high-voltage transistor and method for its preparation
04/17/2014DE102013111375A1 Transistorbauelement und verfahren zum herstellen einestransistorbauelements Transistor device and method of manufacturing a transistor device
04/17/2014DE102013104019A1 Method for forming p-type FET (pFET) structure, involves forming germanium-channel implant region in n-type wall, through opening of mask layer formed on semiconductor substrate
04/17/2014DE102010028463B4 Verfahren zur Herstellung eines Halbleiterbauelements mit komplexen leitenden Elementen in einem dielektrischen Materialsystem unter Anwendung einer Barrierenschicht und Halbleiterbauelement diese aufweisend A process for producing a semiconductor device with conductive elements in a complex dielectric material system using a barrier layer and this semiconductor device comprising
04/16/2014EP2720369A1 Thermoelectric conversion device
04/16/2014EP2720273A1 tunneling field-effect transistor including graphene channel
04/16/2014EP2720272A2 High electron mobility transistor and method of driving the same
04/16/2014EP2720271A1 Thin film transistor and method for manufacturing the same, array substrate, and display device
04/16/2014EP2720270A1 Field plate assisted resistance reduction in a semiconductor device
04/16/2014EP2720269A1 Semiconductor device
04/16/2014EP2720263A1 Semiconductor device
04/16/2014EP2720257A1 Semiconductor element, hemt element, and method for manufacturing semiconductor element
04/16/2014EP2720256A2 Strained semiconductor device
04/16/2014EP2720255A1 Method for manufacturing silicon carbide semiconductor device
04/16/2014EP2720254A1 Semiconductor device and method for producing same
04/16/2014EP2719794A2 Plasma etching of diamond surfaces
04/16/2014CN203553176U Multi-chip diode