Patents
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
01/2006
01/19/2006US20060014342 Method of manufacturing a semiconductor component
01/19/2006US20060014339 Method of detecting one or more defects in a string of spaced apart studs
01/19/2006US20060014338 Method and structure for strained finfet devices
01/19/2006US20060014337 Semiconductor device and method for manufacturing the same
01/19/2006US20060014336 Method of forming double-gated silicon-on-insulator (SOI) transistors with corner rounding
01/19/2006US20060014335 Method of manufacturing a semiconductor device
01/19/2006US20060014332 SOI device having increased reliability and reduced free floating body effects
01/19/2006US20060014329 Nanodots formed on silicon oxide and method of manufacturing the same
01/19/2006US20060014317 Integrated circuit package having reduced interconnects
01/19/2006US20060014307 Ferroelectric random access memory capacitor and method for manufacturing the same
01/19/2006US20060014203 carbon nanotubes as electrodes; for biopolymers such as DNA and RNA
01/19/2006US20060014202 production method of electrical connection structure and electric wiring; carbon nanotube as the electrode and contacting the electrode with the biopolymer (DNA, RNA, or a protein) then applying an electric current between the electrode and biopolymer
01/19/2006US20060012728 Display device and method for repairing line disconnection thereof
01/19/2006US20060012727 Liquid crystal display device and method of making same
01/19/2006US20060012294 Electroluminescent devices and displays with integrally fabricated address and logic devices fabricated by printing or weaving
01/19/2006US20060012050 Semiconductor device, designing method thereof, and recording medium storing semicondcutor designing program
01/19/2006US20060012013 Columnar structured material and method of manufacturing the same
01/19/2006US20060012011 Mehtod for processing nitride semiconductor crystal surface and nitride semiconductor crystal obtained by such method
01/19/2006US20060012010 Epitaxial growing method and substrate for epitaxial growth
01/19/2006US20060012009 Semiconductor device
01/19/2006US20060012008 Resistance variable memory device and method of fabrication
01/19/2006US20060012007 Open pattern inductor
01/19/2006US20060012006 Capacitors integrated with inductive components
01/19/2006US20060012004 STI liner for SOI structure
01/19/2006US20060012003 Seal ring for mixed circuitry semiconductor devices
01/19/2006US20060012000 Thin-film transistors based on tunneling structures and applications
01/19/2006US20060011999 Magnetic field sensor comprising a hall element
01/19/2006US20060011998 Electromechanical electron transfer devices
01/19/2006US20060011997 Electrostatic discharge protection of a capacitive type fingerprint sensing
01/19/2006US20060011996 Semiconductor structure including silicide regions and method of making same
01/19/2006US20060011995 Method of forming an oxide film
01/19/2006US20060011994 Damascene replacement metal gate process with controlled gate profile and length using Si1-xGex as sacrificial material
01/19/2006US20060011993 Junction interconnection structures
01/19/2006US20060011992 Capacitor layout orientation
01/19/2006US20060011991 Non-volatile semiconductor memory device and method of manufacturing the same
01/19/2006US20060011990 Method for fabricating strained semiconductor structures and strained semiconductor structures formed thereby
01/19/2006US20060011989 Semiconductor device including metal insulator semiconductor field effect transistor and method of manufacturing the same
01/19/2006US20060011988 Integrated circuit with multiple spacer insulating region widths
01/19/2006US20060011987 Method for fabricating a p-type shallow junction using diatomic arsenic
01/19/2006US20060011986 Semiconductor device and method for manufacturing the same
01/19/2006US20060011985 Asymmetric hetero-doped high-voltage MOSFET (AH2MOS)
01/19/2006US20060011984 Control of strain in device layers by selective relaxation
01/19/2006US20060011983 Methods of fabricating strained-channel FET having a dopant supply region
01/19/2006US20060011982 Micro-mechanically strained semiconductor film
01/19/2006US20060011981 High frequency MOS transistor, method of forming the same, and method of manufacturing a semiconductor device including the same
01/19/2006US20060011978 Semiconductor constructions and integrated circuits
01/19/2006US20060011976 Termination for trench MIS device having implanted drain-drift region
01/19/2006US20060011975 Semiconductor device and manufacturing method for the same
01/19/2006US20060011974 Drain-extended MOS transistors with diode clamp and methods for making the same
01/19/2006US20060011973 Semiconductor device
01/19/2006US20060011972 Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell
01/19/2006US20060011971 Nonvolatile semiconductor memory device and method of manufacturing the same
01/19/2006US20060011970 Field-effect transistors having doped aluminum oxide dielectrics
01/19/2006US20060011969 Use of dilute steam ambient for improvement of flash devices
01/19/2006US20060011968 Semiconductor devices and methods of forming the same
01/19/2006US20060011967 Split gate memory structure and manufacturing method thereof
01/19/2006US20060011966 Structure of a non-volatile memory cell and method of forming the same
01/19/2006US20060011965 Non-volatile flash memory device having at least two different channel concentrations and method of fabricating the same
01/19/2006US20060011964 Semiconductor device and method for fabricating the same
01/19/2006US20060011963 Method and apparatus for interconnecting electrodes with partial titanium coating
01/19/2006US20060011962 Accumulation device with charge balance structure and method of forming the same
01/19/2006US20060011960 Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage
01/19/2006US20060011959 Semiconductor devices having a planarized insulating layer and methods of forming the same
01/19/2006US20060011958 Magnetic random access memory with bit line and/or digit line magnetic layers
01/19/2006US20060011951 Process for fabricating non-volatile memory by tilt-angle ion implantation
01/19/2006US20060011950 Semiconductor device and method of manufacturing the same
01/19/2006US20060011947 Semiconductor structures and memory device constructions
01/19/2006US20060011940 Thyristor-type memory device
01/19/2006US20060011939 Two-dimensional silicon controlled rectifier
01/19/2006US20060011938 Super lattice tunnel junctions
01/19/2006US20060011936 Fluorescent substance containing nitrogen, method for manufacturing the same, and light-emitting device
01/19/2006US20060011934 Semiconductor light-emitting element and manufacturing method thereof
01/19/2006US20060011927 Organic light emitting devices and electroluminescent display panel applying the same
01/19/2006US20060011925 Radiation-emitting semiconductor element and method for producing the same
01/19/2006US20060011924 Monolithic vertical junction field effect transistor and schottky barrier diode fabricated from silicon carbide and method for fabricating the same
01/19/2006US20060011923 Electromagnetic radiation generating semiconductor chip and method for making same
01/19/2006US20060011922 Light-emitting device comprising an eu(II)-activated phosphor
01/19/2006US20060011921 Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films
01/19/2006US20060011920 Thin film transistor array panel and manufacturing method thereof
01/19/2006US20060011919 Vertical gate device for an image sensor and method of forming the same
01/19/2006US20060011918 Flat panel display device and method of manufacturing the same
01/19/2006US20060011917 Thin film transistor, flat panel display device therewith, and method of manufacturing the thin film transistor
01/19/2006US20060011916 Substrate for epitaxial growth, process for producing the same, and multi-layered film structure
01/19/2006US20060011915 Nitride semiconductor device
01/19/2006US20060011914 Novel conductive elements for thin film transistors used in a flat panel display
01/19/2006US20060011913 Display device mounted with read function and electric appliance
01/19/2006US20060011912 Method of forming a metal pattern and a method of fabricating tft array panel by using the same
01/19/2006US20060011910 PCRAM device with switching glass layer
01/19/2006US20060011909 Organic thin film transistor with polymeric interface
01/19/2006US20060011908 Light emitting element
01/19/2006US20060011907 Compounds containing 3,4-methylenedioxythiophene units
01/19/2006US20060011906 Ion implantation for suppression of defects in annealed SiGe layers
01/19/2006US20060011905 Semiconductor device comprising a superlattice dielectric interface layer
01/19/2006US20060011904 Layered composite film incorporating quantum dots as programmable dopants
01/19/2006US20060011903 Nitride based semiconductor light-emitting device
01/19/2006US20060011894 Material for a functional layer of an organic electronic component, method for the production thereof, and use thereof
01/19/2006DE3900426B4 Verfahren zum Betreiben einer Halbleiteranordnung A method of operating a semiconductor device
01/19/2006DE112004000248T5 UV-Abblockschicht zum Reduzieren der UV-Induzierten Aufladung von SONOS-Doppelbit-Flash-Speicher-Einrichtungen in der Beol-Bearbeitung UV Abblockschicht for reducing UV-induced charging of SONOS dual bit flash memory devices in the Beol processing
01/19/2006DE112004000136T5 Halbleiterbauelement und Verfahren zu dessen Herstellung Semiconductor device and process for its preparation
01/19/2006DE102004031385A1 Verfahren zur Herstellung einer DRAM-Speicherzellenanordnung mit Stegfeldeffekttransistoren und DRAM-Speicherzellenanordnung mit CFETs A method of manufacturing a DRAM memory cell array having fin field effect transistors and DRAM memory cell array with CFETS