Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/1996
05/15/1996EP0712154A2 Process for fabricating high-quality integrated circuits containing passive devices
05/15/1996EP0712153A2 Packaging electrical circuits
05/15/1996EP0712152A1 Semiconductor device and method for its manufacture
05/15/1996EP0712151A1 Method for adjusting the current gain of polysilicon emitter bipolar transistors
05/15/1996EP0712150A1 Sublimation growth of silicon carbide single crystals
05/15/1996EP0712137A2 Programmable semiconductor memory
05/15/1996EP0712136A2 Nonvolatile memory producing apparatus and method
05/15/1996EP0712134A2 Semiconductor memory
05/15/1996EP0711854A1 Epitaxial wafer and method for the preparation thereof
05/15/1996EP0711853A1 Method for growing gallium nitride compound semiconductor crystal, and gallium nitride compound semiconductor device
05/15/1996EP0711846A1 Titanium nitride deposited by chemical vapor deposition
05/15/1996EP0711738A2 Ceramic green sheet and method for producing ceramic substrate
05/15/1996EP0711457A1 A reverse field plate, junction-terminating structure
05/15/1996EP0711456A1 Coated bonding wires in high lead count packages
05/15/1996EP0711455A1 Shadow clamp
05/15/1996EP0711454A1 Method for forming solder bumps
05/15/1996EP0711447A1 Programmable logic device with verify circuitry for classifying fuse link states as validly closed, validly open or invalid
05/15/1996EP0711424A1 Silicon pixel electrode
05/15/1996EP0711420A1 Process of manufacturing a silicon semiconductor substrate with an integrated waveguide coupled to an optical fibre
05/15/1996EP0711363A1 Process for producing high-resistance silicon carbide
05/15/1996EP0711108A1 Device for coating substrates in semiconductor manufacture
05/15/1996EP0556201B1 Semiconductor device with a voltage-limiting region
05/15/1996DE4446489C1 Verfahren zum Manipulieren von Mikrobauteilen und Vorrichtung zur Durchführung des Verfahrens A method of manipulating micro-components and apparatus for carrying out the method
05/15/1996DE4440390A1 Selective epitaxial deposition of differently doped layers
05/15/1996DE4440375A1 Semiconductor component formation on 2 region substrate
05/15/1996DE3745036C2 Bipolar transistor combined with FET or photodiode
05/15/1996DE19542240A1 Semiconductor device for static random access memory
05/15/1996DE19507279A1 Semiconductor component insulating method for e.g. LOCOS-processed component
05/15/1996DE19504434C1 Structured mask layer mfr. for dry-etching process
05/15/1996CN1122519A Electrostatic discharge protection device and method of forming
05/15/1996CN1122517A Producing method of semiconductor diode with laminar material strecture
05/14/1996US5517594 Thermal reactor optimization
05/14/1996US5517515 Multichip module with integrated test circuitry disposed within interposer substrate
05/14/1996US5517456 Semiconductor memory device including a word line driving circuit of the divisional decoding type
05/14/1996US5517443 Method and system for protecting a stacked gate edge in a semi-conductor device from self aligned source (SAS) etch in a semi-conductor device
05/14/1996US5517442 Random access memory and an improved bus arrangement therefor
05/14/1996US5517342 Liquid crystal display having additional capacitors formed from pixel electrodes and a method for manufacturing the same
05/14/1996US5517280 Photolithography system
05/14/1996US5517224 Semiconductor device for driving heat generator
05/14/1996US5517126 For measuring electrical characteristics of an object to be tested
05/14/1996US5517107 On-chip variance detection for integrated circuit devices
05/14/1996US5517062 Stress released VLSI structure by the formation of porous intermetal layer
05/14/1996US5517061 CMOS read only memory with programming at the second metal layer on a two-metal process
05/14/1996US5517060 Semiconductor device having improved backing conductive layers
05/14/1996US5517059 Electron and laser beam welding apparatus
05/14/1996US5517057 Electronic modules with interconnected surface metallization layers
05/14/1996US5517056 Molded carrier ring leadframe having a particular resin injecting area design for gate removal and semiconductor device employing the same
05/14/1996US5517050 Semiconductor integrated circuit device having component transistor with protected gate electrode
05/14/1996US5517048 Pad structure with parasitic MOS transistor for use with semiconductor devices
05/14/1996US5517047 Bonded wafer processing
05/14/1996US5517045 Nitride cap sidewell oxide protection from BOE etch
05/14/1996US5517044 Non-volatile semiconductor memory device having thin film transistors equipped with floating gates
05/14/1996US5517042 Semiconductor device having multi-level wiring structure
05/14/1996US5517040 Personalizable semiconductor chips for analog and analog/digital circuits
05/14/1996US5517038 Semiconductor device including three-dimensionally disposed logic elements for improving degree of integration
05/14/1996US5517036 Tape carrier, and test apparatus for the same
05/14/1996US5517001 High performance horizontal diffusion furnace system
05/14/1996US5516983 Polymer electric device
05/14/1996US5516886 Removing metal ions with ion exchange resin, washing resin with polyacrylic acid, fluorinated carboxylic acid
05/14/1996US5516732 Wafer processing machine vacuum front end method and apparatus
05/14/1996US5516731 High-temperature bias anneal of integrated circuits for improved radiation hardness and hot electron resistance
05/14/1996US5516730 Pre-thermal treatment cleaning process of wafers
05/14/1996US5516729 Method for planarizing a semiconductor topography using a spin-on glass material with a variable chemical-mechanical polish rate
05/14/1996US5516728 Process for fabircating an integrated circuit
05/14/1996US5516726 Method of manufacturing local interconnection for semiconductors
05/14/1996US5516725 Contact alloy having capacity when in combination with a substrate compound to exist as a two phase binary equilibrium reciprocal system; sputtering; annealing
05/14/1996US5516724 Oxidizing methods for making low resistance source/drain germanium contacts
05/14/1996US5516722 Method for increasing doping uniformity in a flow flange reactor
05/14/1996US5516721 Isolation structure using liquid phase oxide deposition
05/14/1996US5516720 Stress relaxation in dielectric before metallization
05/14/1996US5516719 Method for the fabrication of a capacitor in a semiconductor device
05/14/1996US5516718 Method of making BI-CMOS integrated circuit having a polysilicon emitter
05/14/1996US5516716 Method of making a charge coupled device with edge aligned implants and electrodes
05/14/1996US5516713 Method of making high coupling ratio NAND type flash memory
05/14/1996US5516712 Method of fabricating radiation imager with single passivation dielectric for transistor and diode
05/14/1996US5516711 Method for forming LDD CMOS with oblique implantation
05/14/1996US5516710 Method of forming a transistor
05/14/1996US5516709 Method of manufacturing bipolar transistor with reduced numbers of steps without increasing collector resistance
05/14/1996US5516708 Method of making single polysilicon self-aligned bipolar transistor having reduced emitter-base junction
05/14/1996US5516707 Large-tilted-angle nitrogen implant into dielectric regions overlaying source/drain regions of a transistor
05/14/1996US5516706 Method of manufacturing semiconductor device with a gettering sink material layer
05/14/1996US5516705 Method of forming four layer overvoltage protection device
05/14/1996US5516626 Resist processing method
05/14/1996US5516625 Fill and etchback process using dual photoresist sacrificial layer and two-step etching process for planarizing oxide-filled shallow trench structure
05/14/1996US5516608 Method for controlling a line dimension arising in photolithographic processes
05/14/1996US5516605 Photo mask provided with development rate measuring pattern and method for measuring development rate uniformity
05/14/1996US5516596 A coating of hydrogen silsesquisiloxane resin on refractory fibers, heat treatment to form ceramics
05/14/1996US5516589 Silicon carbide thin film circuit element and method of manufacturing the same
05/14/1996US5516404 Method for manufacturing a micro-electronic component having an electrically conductive tip of doped silicon
05/14/1996US5516403 Reversing orientation of sputtering screen to avoid contamination
05/14/1996US5516400 Techniques for assembling polishing pads for chemical-mechanical polishing of silicon wafers
05/14/1996US5516399 Monitoring electrical characteristics between two electrodesproximate to but not in contact with at least one wafer
05/14/1996US5516369 Method and apparatus for particle reduction from semiconductor wafers
05/14/1996US5516367 Chemical vapor deposition chamber with a purge guide
05/14/1996US5516366 Supply control system for semiconductor process gasses
05/14/1996US5516363 Specially doped precursor solutions for use in methods of producing doped ABO3 -type average perovskite thin-film capacitors
05/14/1996US5516346 Slurries for chemical mechanical polishing
05/14/1996US5516283 Apparatus for processing a plurality of circular wafers
05/14/1996US5516251 Magazine carrying apparatus
05/14/1996US5516125 Baffled collet for vacuum pick-up of a semiconductor die
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