Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2004
06/15/2004US6750498 Semiconductor device including memory cells and manufacturing method thereof
06/15/2004US6750496 Manufacturing method of semiconductor integrated circuit device, and semiconductor integrated circuit device
06/15/2004US6750495 Damascene capacitors for integrated circuits
06/15/2004US6750494 Semiconductor buried contact with a removable spacer
06/15/2004US6750493 Semiconductor storage device including nonvolatile ferroelectric memory
06/15/2004US6750492 Semiconductor memory with hydrogen barrier
06/15/2004US6750491 Magnetic memory device having soft reference layer
06/15/2004US6750487 Dual double gate transistor
06/15/2004US6750486 Silicon substrate; n-channel region with silicon-germanium buffer layer, silicon-germanium compound relax layer, silicon epitaxial layer; p-channel region with silicon-germanium compound layer and silicon epitaxial cap layer
06/15/2004US6750484 Silicon germanium hetero bipolar transistor
06/15/2004US6750483 Silicon-germanium bipolar transistor with optimized germanium profile
06/15/2004US6750482 Highly conductive semiconductor layer having two or more impurities
06/15/2004US6750481 Semiconductor laminated substrate, semiconductor crystal substrate and semiconductor device and method of manufacturing the same
06/15/2004US6750480 Bipolar transistor with lattice matched base layer
06/15/2004US6750479 Semiconductor component and a method for identifying a semiconductor component
06/15/2004US6750476 Substrate device manufacturing method and substrate device, electrooptical device manufacturing method and electrooptical device and electronic unit
06/15/2004US6750475 Method for fabricating electric interconnections and interconnection substrate having electric interconnections fabricated by the same method
06/15/2004US6750474 Semiconducting devices and method of making thereof
06/15/2004US6750471 Microelectronic device including transistor with source and drain region separated by channel region comprising molecule having closed hollow cage structure which conducts electrons, exhibits coulomb blockage and receives and transmits electrons
06/15/2004US6750464 Having pattern elements defined as apertures in stencil reticle, each element split into portions separated by girders formed from membrane of reticle and configured for transfer to substrate using single exposure shot of charged particle beam
06/15/2004US6750462 Ion implanting method and apparatus
06/15/2004US6750423 Laser irradiation method, laser irradiation apparatus, and method of manufacturing a semiconductor device
06/15/2004US6750159 Semiconductor apparatus, manufacturing method therefor, solid state image device and manufacturing method therefor
06/15/2004US6750158 Method for producing a semiconductor device
06/15/2004US6750157 Nonvolatile memory cell with a nitridated oxide layer
06/15/2004US6750155 Methods to minimize moisture condensation over a substrate in a rapid cycle chamber
06/15/2004US6750154 Gas assisted method for applying resist stripper and gas-resist stripper combinations
06/15/2004US6750153 Process for producing macroscopic cavities beneath the surface of a silicon wafer
06/15/2004US6750151 Etching method for ZnSe polycrystalline substrate
06/15/2004US6750150 Method for reducing dimensions between patterns on a photoresist
06/15/2004US6750149 Method of manufacturing electronic device
06/15/2004US6750147 Process for integration of a trench for capacitors and removal of black silicon
06/15/2004US6750146 Method for forming barrier layer
06/15/2004US6750145 Method of eliminating agglomerate particles in a polishing slurry
06/15/2004US6750144 Method for electrochemical metallization and planarization of semiconductor substrates having features of different sizes
06/15/2004US6750143 Method for forming a plating film, and device for forming the same
06/15/2004US6750142 Semiconductor device and method for manufacturing the same
06/15/2004US6750141 Silicon carbide cap layers for low dielectric constant silicon oxide layers
06/15/2004US6750140 Process for producing contact holes on a metallization structure
06/15/2004US6750139 Dummy metal pattern method and apparatus
06/15/2004US6750138 Multilayer wires laminated to integrated circuit chip; applying electrode, dielectric; pressurization
06/15/2004US6750137 Method and apparatus for forming an interlayer insulating film and semiconductor device
06/15/2004US6750136 Contact structure production method
06/15/2004US6750135 Method for forming chip scale package
06/15/2004US6750134 Variable cross-section plated mushroom with stud for bumping
06/15/2004US6750133 Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps
06/15/2004US6750132 Flip chip package, circuit board thereof and packaging method thereof
06/15/2004US6750130 Heterointegration of materials using deposition and bonding
06/15/2004US6750128 Methods of polishing, interconnect-fabrication, and producing semiconductor devices
06/15/2004US6750127 Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance
06/15/2004US6750126 Methods for sputter deposition of high-k dielectric films
06/15/2004US6750125 Semiconductor device and method for manufacturing the same, semiconductor wafer and semiconductor device manufactured thereby
06/15/2004US6750124 Direct patterning of nanometer-scale silicide structures on silicon by ion-beam implantation through a thin barrier layer
06/15/2004US6750123 Method of manufacturing CMOS device with implantation shielding layer
06/15/2004US6750122 Semiconductor device formed with an oxygen implant step
06/15/2004US6750121 Apparatus and method for forming single crystalline nitride substrate using hydride vapor phase epitaxy and laser beam
06/15/2004US6750120 Method and apparatus for MOCVD growth of compounds including GaAsN alloys using an ammonia precursor with a catalyst
06/15/2004US6750118 Process and apparatus to subdivide objects
06/15/2004US6750117 Shallow trench isolation process
06/15/2004US6750116 Method for fabricating asymmetric inner structure in contacts or trenches
06/15/2004US6750115 Method for generating alignment marks for manufacturing MIM capacitors
06/15/2004US6750114 One-mask metal-insulator-metal capacitor and method for forming same
06/15/2004US6750113 Metal-insulator-metal capacitor in copper
06/15/2004US6750112 Method of forming a bitline and a bitline contact, and dynamic memory cell including a bitline and bitline made contact according to the method
06/15/2004US6750111 Method for fabricating a trench capacitor
06/15/2004US6750110 Continuous good step coverage CVD platinum metal deposition
06/15/2004US6750109 Halo-free non-rectifying contact on chip with halo source/drain diffusion
06/15/2004US6750108 Method for manufacturing a semiconductor device
06/15/2004US6750107 Method and apparatus for isolating a SRAM cell
06/15/2004US6750106 Polysilicon gate doping level variation for reduced leakage current
06/15/2004US6750105 Method of fabricating a high-voltage transistor with a multi-layered extended drain structure
06/15/2004US6750104 Doping with phosphorus or boron
06/15/2004US6750103 NROM cell with N-less channel
06/15/2004US6750100 Nano-meter memory device and method of making the same
06/15/2004US6750099 Method for fabricating capacitor of semiconductor device
06/15/2004US6750098 Integrated semiconductor memory and fabrication method
06/15/2004US6750097 Method of fabricating a patterened SOI embedded DRAM/eDRAM having a vertical device cell and device formed thereby
06/15/2004US6750096 Trench capacitor with buried plate and method for its production
06/15/2004US6750095 Integrated circuit with vertical transistors
06/15/2004US6750093 Semiconductor integrated circuit and method for manufacturing the same
06/15/2004US6750092 Methods of forming ruthenium film by changing process conditions during chemical vapor deposition and ruthenium films formed thereby
06/15/2004US6750091 Diode formation method
06/15/2004US6750089 Methods of forming conductive interconnects
06/15/2004US6750088 SOI MOS field effect transistor and manufacturing method therefor
06/15/2004US6750087 Thin film transistor array, fabrication method thereof, and liquid crystal display device employing the same
06/15/2004US6750086 Semiconductor device having a semiconductor thin film containing low concentration of unbound hydrogen atoms and method of manufacturing the same
06/15/2004US6750083 Method of masking microelectronic semiconductor chips with protective caps
06/15/2004US6750080 Semiconductor device and process for manufacturing the same
06/15/2004US6750076 Fabrication of a microchip-based electrospray device
06/15/2004US6750075 Multi color detector
06/15/2004US6750074 Method of manufacturing a semiconductor device and a method for fixing the semiconductor device using substrate jig
06/15/2004US6750073 Method for forming a mask pattern
06/15/2004US6750072 Method for micro-fabricating a pixelless infrared imaging device
06/15/2004US6750069 Minimally spaced MRAM structures
06/15/2004US6750068 Method of fabricating a magnetic element with an improved magnetoresistance ratio with an antiparallel top and bottom pinned ferromagnetic layer
06/15/2004US6750067 Microelectronic piezoelectric structure and method of forming the same
06/15/2004US6750066 Precision high-K intergate dielectric layer
06/15/2004US6750000 Electron device manufacturing method, a pattern forming method, and a photomask used for those methods
06/15/2004US6749998 Reactive double bonds, hydrazines, oximes, hydroquinone, pyrogallol, gallic acid, thiols, aldehydes, butyrophenones, hydroxytoluenes, 3-tert-butyl-4-hydroxy anisole, tocopherol, 6-hydroxy-2,5,7,8-tetramethylchroman-2-carboxylic acid
06/15/2004US6749991 Negative-working photoresist composition