Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
02/2005
02/10/2005WO2004109807A3 Semiconductor structure comprising integrated doping channels
02/10/2005WO2004100261A3 Semiconductor wafer, panel and electronic component comprising stacked semiconductor chips, and method for the production thereof
02/10/2005WO2004095477A3 High-performance electrostatic clamp comprising a resistive layer, micro-grooves, and dielectric layer
02/10/2005WO2004093197A3 Method for forming structures in finfet devices
02/10/2005WO2004091808A3 Ultraphobic surface for high pressure liquids
02/10/2005WO2004090941A3 Integrated circuit die having a copper contact and method therefor
02/10/2005WO2004079796A3 Atomic layer deposited dielectric layers
02/10/2005WO2004079779A3 A method of patterning photoresist on a wafer using an attenuated phase shift mask
02/10/2005WO2004075294A3 Flip-chip component packaging process and flip-chip component
02/10/2005WO2004070792A3 Thin multiple semiconductor die package
02/10/2005WO2004068539A3 Sidewall structure and method of fabrication for reducing oxygen diffusion to contact plugs during cw hole reactive ion etch processing
02/10/2005WO2004048230A3 Vertical carousel with top and side access stations
02/10/2005WO2004040627A3 Electronic components
02/10/2005WO2004014785A3 Method for producing at least one small opening in a layer on a substrate and components produced according to said method
02/10/2005WO2002084714A3 Method and apparatus for electrochemically depositing a material onto a workpiece surface
02/10/2005US20050034096 Method of identifying an extreme interaction pitch region, methods of designing mask patterns and manufacturing masks, device manufacturing methods and computer programs
02/10/2005US20050034093 Semiconductor integrated circuit device and method for designing the same
02/10/2005US20050033538 Inspection method and its apparatus, inspection system
02/10/2005US20050033467 Dynamic metrology sampling methods, and system for performing same
02/10/2005US20050033465 Remote maintenance method, industrial device, and semiconductor device
02/10/2005US20050033463 Method, computer program product and apparatus for scheduling maintenance actions in a substrate processing system
02/10/2005US20050033197 Apparatus for fluid transport and related method thereof
02/10/2005US20050032659 Organic solvent, sugar, water and such as n-methylethanolamine; suppressing corrosion; gallium arsenide semiconductors; quality, low cost integrated circuits
02/10/2005US20050032658 Monoethanolamine and dimethylacetamide; cleanly eliminates thick films; nondamaging
02/10/2005US20050032657 Stripping and cleaning compositions for microelectronics
02/10/2005US20050032395 Methods for forming porous insulator structures on semiconductor devices
02/10/2005US20050032394 Method for improving thickness uniformity of deposited ozone-TEOS silicate glass layers
02/10/2005US20050032393 Method of composite gate formation
02/10/2005US20050032392 Method to improve adhesion of dielectric films in damascene interconnects
02/10/2005US20050032391 Method for processing a semiconductor wafer
02/10/2005US20050032390 Microfeature workpiece processing system for, e.g., semiconductor wafer analysis
02/10/2005US20050032389 Method for avoiding erosion of DRAM fuse sidewall
02/10/2005US20050032388 Etching of high aspect ration structures
02/10/2005US20050032387 Asymmetric plating
02/10/2005US20050032386 Etching and plasma treatment process to improve a gate profile
02/10/2005US20050032384 Method of creating a photonic via using deposition
02/10/2005US20050032383 Method for producing light emitting diode
02/10/2005US20050032382 Staggered in-situ deposition and etching of a dielectric layer for HDP CVD
02/10/2005US20050032381 Method and apparatus for polishing metal and dielectric substrates
02/10/2005US20050032376 Silicon wafer and process for producing it
02/10/2005US20050032375 Methods for electrochemically fabricating structures using adhered masks, incorporating dielectric sheets, and/or seed layers that are partially removed via planarization
02/10/2005US20050032373 Photoresists and methods for use thereof
02/10/2005US20050032372 Methods for forming a thin film on an integrated circuit device by sequentially providing energies to activate the reactants
02/10/2005US20050032371 Method for manufacturing a semiconductor device
02/10/2005US20050032369 Two step method for filling holes with copper
02/10/2005US20050032368 Method to form copper seed layer for copper interconnect
02/10/2005US20050032367 Passivation processes for use with metallization techniques
02/10/2005US20050032366 Methods of forming metal-comprising materials and capacitor electrodes; and capacitor constructions
02/10/2005US20050032365 Atomic layer deposition of metal during the formation of a semiconductor device
02/10/2005US20050032364 Method of forming tungsten film
02/10/2005US20050032363 Method for manufacturing a semiconductor device
02/10/2005US20050032362 Electrochemical fabrication methods including use of surface treatments to reduce overplating and/or planarization during formation of multi-layer three-dimensional structures
02/10/2005US20050032361 High aspect ratio contact structure with reduced silicon consumption
02/10/2005US20050032360 Systems and methods of forming refractory metal nitride layers using disilazanes
02/10/2005US20050032359 Damascene gate process
02/10/2005US20050032358 Semiconductor device and method for fabricating the same
02/10/2005US20050032356 Semiconductor device and method of manufacturing the same
02/10/2005US20050032355 Dual damascene method for ultra low K dielectrics
02/10/2005US20050032354 Method for selectively controlling damascene CD bias
02/10/2005US20050032353 Method for reducing defects in post passivation interconnect process
02/10/2005US20050032352 H2 plasma treatment
02/10/2005US20050032351 Chip structure and process for forming the same
02/10/2005US20050032350 Topography controlled interconnects
02/10/2005US20050032349 Low fabrication cost, fine pitch and high reliability solder bump
02/10/2005US20050032348 Method of wafer bumping for enabling a stitch wire bond in the absence of discrete bump formation
02/10/2005US20050032346 Stud electrode and process for making same
02/10/2005US20050032345 Group III-nitride growth on Si substrate using oxynitride interlayer
02/10/2005US20050032343 Method for avoiding short-circuit of conductive wires
02/10/2005US20050032342 Atomic layer deposition of CMOS gates with variable work functions
02/10/2005US20050032341 Doping apparatus, doping method, and method for fabricating thin film transistor
02/10/2005US20050032340 Semiconductor device and method of manufacturing the same
02/10/2005US20050032339 Substrate of semiconductor device and fabrication method thereof as well as semiconductor device and fabrication method thereof
02/10/2005US20050032338 Fabricating method of low temperature poly-silicon film and low temperature poly-silicon thin film transistor
02/10/2005US20050032337 Method and apparatus for forming a silicon wafer with a denuded zone
02/10/2005US20050032336 Method of manufacturing a semiconductor device
02/10/2005US20050032335 Method to chemically remove metal impurities from polycide gate sidewalls
02/10/2005US20050032334 Semiconductor device and method for manufacturing the same
02/10/2005US20050032333 Wafer thinning using magnetic mirror plasma
02/10/2005US20050032332 Method for separating semiconductor wafer from supporting member, and apparatus using the same
02/10/2005US20050032331 Soi wafer manufacturing method and soi wafer
02/10/2005US20050032330 Methods for transferring a useful layer of silicon carbide to a receiving substrate
02/10/2005US20050032329 Method of transferring devices
02/10/2005US20050032328 Chemical mechanical polishing in forming semiconductor device
02/10/2005US20050032327 Fabrication method and device structure of shallow trench insulation for silicon wafer containing silicon-germanium
02/10/2005US20050032326 Methods of forming hemispherical grained silicon on a template on a semiconductor work object
02/10/2005US20050032325 Methods of forming capacitors
02/10/2005US20050032324 Method for fabricating a trench structure which is electrically connected to a substrate on one side via a buried contact
02/10/2005US20050032323 Flat profile structures for bipolar transistors
02/10/2005US20050032322 Metal oxide semiconductor (MOS) transistors having three dimensional channels and methods of fabricating the same
02/10/2005US20050032321 Strained silicon MOS devices
02/10/2005US20050032320 Method for manufacturing a semiconductor device and a semiconductor device manufactured thereby
02/10/2005US20050032319 Controlling the location of conduction breakdown in phase change memories
02/10/2005US20050032318 Method for making a semiconductor device having a high-k gate dielectric
02/10/2005US20050032317 Methods of forming material on a substrate, and a method of forming a field effect transistor gate oxide on a substrate
02/10/2005US20050032316 Cross diffusion barrier layer in polysilicon
02/10/2005US20050032315 Semiconductor device and method of manufacturing the same
02/10/2005US20050032314 Dopant barrier for doped glass in memory devices
02/10/2005US20050032312 Non-volatile memory device
02/10/2005US20050032311 Fabrication method for memory cell
02/10/2005US20050032310 Semiconductor memory device and manufacturing method thereof
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