Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
02/2005
02/15/2005US6855989 Damascene finfet gate with selective metal interdiffusion
02/15/2005US6855988 Semiconductor switching devices
02/15/2005US6855987 Semiconductor device with high mobility and high speed
02/15/2005US6855986 Termination structure for trench DMOS device and method of making the same
02/15/2005US6855985 Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
02/15/2005US6855984 Process to reduce gate edge drain leakage in semiconductor devices
02/15/2005US6855982 Self aligned double gate transistor having a strained channel region and process therefor
02/15/2005US6855981 Silicon carbide power device having protective diode
02/15/2005US6855980 Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling
02/15/2005US6855979 Multi-bit non-volatile memory device and method therefor
02/15/2005US6855978 Gate-contact structure and method for forming the same
02/15/2005US6855976 Semiconductor device using partial SOI substrate and manufacturing method thereof
02/15/2005US6855974 Ferroelectric capacitor, process for production thereof and semiconductor device using the same
02/15/2005US6855973 Semiconductor memory device including a capacitor an upper electrode of which being resistant of exfoliation
02/15/2005US6855972 Composite integrated circuit and its fabrication method
02/15/2005US6855971 Haze-free BST films
02/15/2005US6855969 Semiconductor device having a plurality of gate electrodes and manufacturing method thereof
02/15/2005US6855966 Floating gate and fabricating method of the same
02/15/2005US6855965 Method of manufacturing a semiconductor component and semiconductor component thereof
02/15/2005US6855964 Triggering of an ESD NMOS through the use of an N-type buried layer
02/15/2005US6855963 Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate
02/15/2005US6855960 Flat panel display with black matrix and method of fabricating thereof
02/15/2005US6855957 Semiconductor device and manufacturing method thereof
02/15/2005US6855956 Semiconductor thin film and semiconductor device
02/15/2005US6855955 Thin film transistor array panel
02/15/2005US6855954 Thin film transistor, fabrication method thereof and liquid crystal display having the thin film transistor
02/15/2005US6855953 Electronic circuit assembly having high contrast fiducial
02/15/2005US6855952 Semiconductor device and semiconductor package
02/15/2005US6855949 Composition, method and electronic device
02/15/2005US6855943 Droplet target delivery method for high pulse-rate laser-plasma extreme ultraviolet light source
02/15/2005US6855930 Defect inspection apparatus and defect inspection method
02/15/2005US6855916 Wafer temperature trajectory control method for high temperature ramp rate applications using dynamic predictive thermal modeling
02/15/2005US6855908 Glass substrate and leveling thereof
02/15/2005US6855893 Wiring board, semiconductor device, electronic device, and circuit board for electronic parts
02/15/2005US6855885 Electrical component housing
02/15/2005US6855649 Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
02/15/2005US6855648 Method of reducing stress migration in integrated circuits
02/15/2005US6855647 Custom electrodes for molecular memory and logic devices
02/15/2005US6855646 Plasma polymerized electron beam resist
02/15/2005US6855645 Silicon carbide having low dielectric constant
02/15/2005US6855643 Method for fabricating a gate structure
02/15/2005US6855642 Method for fabricating semiconductor integrated circuit device
02/15/2005US6855641 CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof
02/15/2005US6855640 Apparatus and process for bulk wet etch with leakage protection
02/15/2005US6855639 Precise patterning of high-K films
02/15/2005US6855638 Process to pattern thick TiW metal layers using uniform and selective etching
02/15/2005US6855635 Coated doped oxides
02/15/2005US6855634 Polishing method and polishing apparatus
02/15/2005US6855633 Method for fabricating semiconductor device
02/15/2005US6855632 Cu film deposition equipment of semiconductor device
02/15/2005US6855631 Methods of forming via plugs using an aerosol stream of particles to deposit conductive materials
02/15/2005US6855630 Method for making contact with a doping region of a semiconductor component
02/15/2005US6855629 Method for forming a dual damascene wiring pattern in a semiconductor device
02/15/2005US6855628 Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry
02/15/2005US6855627 Method of using amorphous carbon to prevent resist poisoning
02/15/2005US6855626 Wiring substrate having position information
02/15/2005US6855624 Low-loss on-chip transmission line for integrated circuit structures and method of manufacture
02/15/2005US6855623 Recessed tape and method for forming a BGA assembly
02/15/2005US6855622 Method and apparatus for forming a cavity in a semiconductor substrate using a charged particle beam
02/15/2005US6855621 Method of forming silicon-based thin film, method of forming silicon-based semiconductor layer, and photovoltaic element
02/15/2005US6855620 Method for fabricating Group III nitride compound semiconductor substrates and semiconductor devices
02/15/2005US6855619 Method and device for making substrates
02/15/2005US6855618 Radiation hardened semiconductor device
02/15/2005US6855617 Method of filling intervals and fabricating shallow trench isolation structures
02/15/2005US6855616 Methods for manufacturing semiconductor devices
02/15/2005US6855615 Method of manufacturing semiconductor device having an improved isolation structure
02/15/2005US6855614 Sidewalls as semiconductor etch stop and diffusion barrier
02/15/2005US6855613 Method of fabricating a heterojunction bipolar transistor
02/15/2005US6855612 Method for fabricating a bipolar transistor
02/15/2005US6855611 Fabrication method of an electrostatic discharge protection circuit with a low resistant current path
02/15/2005US6855610 Method of forming self-aligned contact structure with locally etched gate conductive layer
02/15/2005US6855608 Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance
02/15/2005US6855607 Multi-step chemical mechanical polishing of a gate area in a FinFET
02/15/2005US6855606 Semiconductor nano-rod devices
02/15/2005US6855605 Semiconductor device with selectable gate thickness and method of manufacturing such devices
02/15/2005US6855604 Method for fabricating metal-oxide semiconductor transistor
02/15/2005US6855603 Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof
02/15/2005US6855602 Method for forming a box shaped polygate
02/15/2005US6855601 Trench-gate semiconductor devices, and their manufacture
02/15/2005US6855600 Method for manufacturing capacitor
02/15/2005US6855599 Fabrication method of a flash memory device
02/15/2005US6855598 Flash memory cell including two floating gates and an erasing gate
02/15/2005US6855597 DRAM cell
02/15/2005US6855596 Method for manufacturing a trench capacitor having an isolation trench
02/15/2005US6855595 Method for manufacturing a CMOS image sensor having a capacitor's top electrode in contact with a photo-sensing element
02/15/2005US6855594 Methods of forming capacitors
02/15/2005US6855593 Trench Schottky barrier diode
02/15/2005US6855592 Method for manufacturing semiconductor device
02/15/2005US6855591 Nonvolatile memory device having STI structure and method of fabricating the same
02/15/2005US6855590 Method of manufacturing the semiconductor device intended to prevent a leakage current from occuring due to a gate induced drain leakage effect
02/15/2005US6855589 Semiconductor device with elevated source/drain structure and its manufacture method
02/15/2005US6855588 Method of fabricating a double gate MOSFET device
02/15/2005US6855586 Low voltage breakdown element for ESD trigger device
02/15/2005US6855584 Method of manufacturing a semiconductor device
02/15/2005US6855583 Method for forming tri-gate FinFET with mesa isolation
02/15/2005US6855582 FinFET gate formation using reverse trim and oxide polish
02/15/2005US6855581 Method for fabricating a high-voltage high-power integrated circuit device
02/15/2005US6855580 Semiconductor device and manufacturing method thereof
02/15/2005US6855579 Semiconductor device and process for fabrication thereof
02/15/2005US6855578 Vibration-assisted method for underfilling flip-chip electronic devices