Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/2005
03/01/2005US6861863 Inspection apparatus for conductive patterns of a circuit board, and a holder thereof
03/01/2005US6861859 Testing circuits on substrates
03/01/2005US6861855 High density interconnection test connector especially for verification of integrated circuits
03/01/2005US6861849 Capacity measuring device and capacity measuring method
03/01/2005US6861764 Wiring substrate having position information
03/01/2005US6861763 Semiconductor devices having stereolithographically fabricated protective layers thereon through which contact pads are exposed and assemblies including the same
03/01/2005US6861762 Flip chip with novel power and ground arrangement
03/01/2005US6861760 Semiconductor device with stacked-semiconductor chips and support plate
03/01/2005US6861759 Semiconductor apparatus of which reliability of interconnections is improved and manufacturing method of the same
03/01/2005US6861758 Area around a via of a semiconductor interconnect selectively doped with metallic dopants to reduce electromigration without adding unnecessary, performance-degrading resistance; some of the region extends into the electroconductive layer
03/01/2005US6861757 Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device
03/01/2005US6861756 Semiconductor integrated circuit device and fabrication process thereof
03/01/2005US6861755 Semiconductor device
03/01/2005US6861752 Semiconductor device having wiring line with hole, and manufacturing method thereof
03/01/2005US6861751 Etch stop layer for use in a self-aligned contact etch
03/01/2005US6861749 Semiconductor device with bump electrodes
03/01/2005US6861745 Method and apparatus for conducting heat in a flip-chip assembly
03/01/2005US6861744 Multilayer ceramic substrate utilizing an intaglio plate with a plurality of grooves having different depths
03/01/2005US6861742 Wafer level chip size package having rerouting layers
03/01/2005US6861737 Semiconductor device packages having semiconductor chips attached to circuit boards, and stack packages using the same
03/01/2005US6861734 External terminals are arranged/exposed in lines on the package bottom with no resin residue left on; the inclined land electrode is forced into and strongly adheres to the seal sheet when pressure is applied through dies
03/01/2005US6861733 Lead frame wire bonding clamp member
03/01/2005US6861730 Semiconductor device with semiconductor chip formed by using wide gap semiconductor as base material
03/01/2005US6861729 Nitride semiconductor substrate and method for manufacturing the same, and nitride semiconductor device using nitride semiconductor substrate
03/01/2005US6861728 Dielectric stack without interfacial layer
03/01/2005US6861726 Apparatus having trench isolation structure with reduced isolation pad height and edge spacer
03/01/2005US6861724 Semiconductor integrated circuit
03/01/2005US6861719 Device for detecting three-dimensional electromagnetic radiation and method for making same
03/01/2005US6861717 Device for defecting a magnetic field, magnetic field measure and current meter
03/01/2005US6861713 Integrated circuitry comprising insulative collars and integrated circuitry comprising sidewall spacers over a conductive line projecting outwardly from a first insulative material
03/01/2005US6861712 MOSFET threshold voltage tuning with metal gate stack control
03/01/2005US6861710 Light emitting device and method of manufacturing the same
03/01/2005US6861708 Semiconductor memory device having a low potential body section
03/01/2005US6861705 Driver circuits and methods for manufacturing driver circuits
03/01/2005US6861704 Semiconductor device and method for fabricating the same
03/01/2005US6861703 Semiconductor device and method for fabricating the same
03/01/2005US6861701 Trench power MOSFET with planarized gate bus
03/01/2005US6861700 Eeprom with split gate source side injection
03/01/2005US6861699 Non-volatile memory device
03/01/2005US6861698 Array of floating gate memory cells having strap regions and a peripheral logic device region
03/01/2005US6861697 Interconnecting conductive layers of memory devices
03/01/2005US6861696 Structure and method for a two-bit memory cell
03/01/2005US6861695 High-k dielectric materials and processes for manufacturing them
03/01/2005US6861694 Semiconductor device and method for fabricating the same
03/01/2005US6861693 Continuous good step coverage CVD platinum metal deposition
03/01/2005US6861692 Method of manufacturing semiconductor device and semiconductor device
03/01/2005US6861691 Selective polysilicon stud growth
03/01/2005US6861690 Lower electrode contact structure and method of forming the same
03/01/2005US6861689 One transistor DRAM cell structure and method for forming
03/01/2005US6861688 Line configuration for bit lines for contact-connecting at least one memory cell, semiconductor component with a line configuration and method for fabricating a line configuration
03/01/2005US6861687 Electrically programmable resistance cross point memory structure
03/01/2005US6861686 Structure of a CMOS image sensor and method for fabricating the same
03/01/2005US6861685 Floating trap type nonvolatile memory device and method of fabricating the same
03/01/2005US6861684 Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor
03/01/2005US6861682 Laser link structure capable of preventing an upper crack and broadening an energy window of a laser beam, and fuse box using the same
03/01/2005US6861681 On-p-GaAs substrate Zn1-xMgxSySe1-y pin photodiode and on-p-GaAs substrate Zn1-xMgxSySe1-y avalanche photodiode
03/01/2005US6861679 Gallium indium nitride arsenide based epitaxial wafer, a hetero field effect transistor using the wafer, and a method of fabricating the hetero field effect transistor
03/01/2005US6861678 Double diffused vertical JFET
03/01/2005US6861674 Electroluminescent device
03/01/2005US6861671 Thin film transistor liquid crystal display and fabrication method thereof
03/01/2005US6861670 Semiconductor device having multi-layer wiring
03/01/2005US6861668 Thin film transistor (TFT) and method for fabricating the TFT
03/01/2005US6861657 Electron beam exposure mask, electron beam exposure method, method of fabricating semiconductor device, and electron beam exposure apparatus
03/01/2005US6861656 High-luminosity EUV-source devices for use in extreme ultraviolet (soft X-ray) lithography systems and other EUV optical systems
03/01/2005US6861654 Cutting device
03/01/2005US6861651 Electron-optical corrector for eliminating third-order aberations
03/01/2005US6861643 Generating a highly directional and highly dense neutral particle beam from a high-density plasma by neutralizing an ion beam generated by the ion extracting portion; etching of electrical thin films; semiconductors
03/01/2005US6861642 Neutral particle beam processing apparatus
03/01/2005US6861620 Ceramic heater
03/01/2005US6861619 Method and apparatus for preparing semiconductor wafers for measurement
03/01/2005US6861614 S system for the formation of a silicon thin film and a semiconductor-insulating film interface
03/01/2005US6861608 Process and system to package residual quantities of wafer level packages
03/01/2005US6861587 Low stress die attachment
03/01/2005US6861479 Composition and process for the production of a porous layer using the composition
03/01/2005US6861377 Surface treatment method, surface-treated substrate, method for forming film pattern, method for making electro-optical device, electro-optical device, and electronic apparatus
03/01/2005US6861376 Photoresist scum free process for via first dual damascene process
03/01/2005US6861375 Method of fabricating semiconductor device
03/01/2005US6861374 Semiconductor device having patterned SOI structure and method for fabricating the same
03/01/2005US6861373 Vacuum processing method and semiconductor device manufacturing method in which high-frequency powers having mutually different frequencies are applied to at least one electrode
03/01/2005US6861372 Semiconductor device manufacturing method
03/01/2005US6861371 Substrate processing system and substrate processing method
03/01/2005US6861370 Bump formation method
03/01/2005US6861369 Method of forming silicidation blocking layer
03/01/2005US6861368 Array substrate for a liquid crystal display device having an improved contact property and fabricating method thereof
03/01/2005US6861367 Semiconductor processing method using photoresist and an antireflective coating
03/01/2005US6861366 Packaged semiconductor device having stacked die
03/01/2005US6861365 Method and system for forming a semiconductor device
03/01/2005US6861362 Self-aligned contact process implementing bias compensation etch endpoint detection and methods for implementing the same
03/01/2005US6861360 Double-sided polishing process for producing a multiplicity of silicon semiconductor wafers
03/01/2005US6861359 Process for semiconductor apparatus including forming an insulator and a semiconductor film on the backside of the wafer and removing the semiconductor film from the backside
03/01/2005US6861356 Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film
03/01/2005US6861355 Metal plating using seed film
03/01/2005US6861354 Method and structure to reduce defects in integrated circuits and substrates
03/01/2005US6861353 Methods for planarization of metal-containing surfaces using halogens and halide salts
03/01/2005US6861352 Semiconductor structure having an improved pre-metal dielectric stack and method for forming the same
03/01/2005US6861351 Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer
03/01/2005US6861350 Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode
03/01/2005US6861349 Method of forming an adhesion layer with an element reactive with a barrier layer
03/01/2005US6861348 Pre-pattern surface modification of low-k dielectrics
03/01/2005US6861347 Method for forming metal wiring layer of semiconductor device
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