Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
04/2005
04/21/2005WO2005036593A2 Deposition of silicon-containing films from hexachlorodisilane
04/21/2005WO2005036592A2 Control of overlay registration
04/21/2005WO2005036589A2 Position shift detection mark, wafer, and pattern position shift measurement method
04/21/2005WO2005036588A2 Tray with flat bottom reference surface
04/21/2005WO2005036567A2 Stand-alone organic-based passive devices
04/21/2005WO2005036314A2 Method and system of diagnosing a processing system using adaptive multivariate analysis
04/21/2005WO2005036269A1 Radiation-curing composition, method for storing same, method for forming cured film, method for forming pattern, method for using pattern, electronic component, and optical waveguide
04/21/2005WO2005036266A1 Masks, lithography device and semiconductor component
04/21/2005WO2005036240A1 Tunable optical filter with heater on a cte-matched transparent substrate
04/21/2005WO2005036135A1 Inspection method and inspection assisting device of quartz product in semiconductor processing system
04/21/2005WO2005035821A1 Film deposition apparatus having hole-like rotary filter plate for capturing fine particles, and film deposition method
04/21/2005WO2005035678A1 Chemical-mechanical polishing (cmp) slurry and method of planarizing surfaces
04/21/2005WO2005035677A1 Chemical-mechanical polishing (cmp) slurry and method of planarizing computer memory disk surfaces
04/21/2005WO2005035437A2 High-precision feedback control for ion sculpting of solid state features
04/21/2005WO2005035395A1 Bare die tray with flat datum surface
04/21/2005WO2005035147A1 Holder for very thin substrates
04/21/2005WO2005035090A2 An etching method in fabrications of microstructures
04/21/2005WO2005024936A3 Support for vertically-oriented capacitors during the formation of a semiconductor device
04/21/2005WO2005020317A3 Ruthenium layer formation for copper film deposition
04/21/2005WO2005017951A3 Quantum dots, nanocomposite materials with quantum dots, optical devices with quantum dots, and related fabrication methods
04/21/2005WO2005008738A3 SEMI-INSULATING GaN AND METHOD OF MAKING THE SAME
04/21/2005WO2005006413A3 Semiconductor etch speed modification
04/21/2005WO2005006412A3 A method of forming an integrated circuit substrate
04/21/2005WO2004114427A3 MAGNETIC TUNNEL JUNCTION PATTERNING USING SiC OR SiN
04/21/2005WO2004114383A3 Strained-silicon-on-insulator single- and double-gate mosfet and method for forming the same
04/21/2005WO2004100230A3 Method for reducing short channel effects in memory cells and related structure
04/21/2005WO2004088721A3 Optimized model and parameter selection for optical metrology
04/21/2005WO2004088415A3 Photometrically modulated delivery of reagents
04/21/2005WO2004086497A3 Method for producing chip stacks
04/21/2005WO2004073043A3 Semiconductor-on-insulator article and method of making same
04/21/2005WO2004073014A3 Metal reduction in wafer scribe area
04/21/2005WO2004071700A3 Room temperature metal direct bonding
04/21/2005WO2004064139A3 Semiconductor chip stack and method for passivating a semiconductor chip stack
04/21/2005WO2004044953A3 High pressure compatible vacuum check for semiconductor wafer including lift mechanism
04/21/2005WO2004010220A8 Nozzle assembly for applying a liquid to a substrate
04/21/2005WO2004008494A3 Servomotor control system and method in a semiconductor manufacturing environment
04/21/2005WO2003103016A3 Mosfet device having geometry that permits frequent body contact
04/21/2005US20050086626 Electronic circuit designing method and apparatus, and storage medium
04/21/2005US20050086621 Method for processing design data of semiconductor integrated circuit
04/21/2005US20050086618 Apparatus and method for verifying an integrated circuit pattern
04/21/2005US20050086617 Back end of line clone test vehicle
04/21/2005US20050086038 Method and system for determining transistor degradation mechanisms
04/21/2005US20050086024 Semiconductor wafer location sensing via non contact methods
04/21/2005US20050086014 Method for calculating threshold voltage of pocket implant MOSFET
04/21/2005US20050085932 Technique for evaluating a fabrication of a semiconductor component and wafer
04/21/2005US20050085578 Packages with bonding pads connected with bonding wires; terminals; coverings; seam welding; hermetic sealing; using mixture of polymer and fillers; controlling particle sizes
04/21/2005US20050085564 Method and structure for self healing cracks in underfill material between an I/C chip and a substrate bonded together with solder balls
04/21/2005US20050085400 System and method for cleaning semiconductor fabrication equipment parts
04/21/2005US20050085177 Work working method and apparatus, cassette, and unit for printing apparatus
04/21/2005US20050085171 Flat-object holder and method of using the same
04/21/2005US20050085168 Cerium oxide abrasive and method of polishing substrates
04/21/2005US20050085166 Process for chemical-mechanical polishing of metal substrates
04/21/2005US20050085163 Method for preventing edge peeling defect
04/21/2005US20050085099 Method of manufacturing a semiconductor device and a process of a thin film transistor
04/21/2005US20050085098 Method for the deposition of silicon nitride films
04/21/2005US20050085097 Method of fabricating multilayer interconnect wiring structure having low dielectric constant insulator film with enhanced adhesivity
04/21/2005US20050085096 Inclusion of low-k dielectric material between bit lines
04/21/2005US20050085094 Integrated ashing and implant annealing method using ozone
04/21/2005US20050085093 Integrated ashing and implant annealing method
04/21/2005US20050085092 Multi-layer dielectric containing diffusion barrier material
04/21/2005US20050085091 Wafer etching techniques
04/21/2005US20050085090 Method for controlling accuracy and repeatability of an etch process
04/21/2005US20050085089 Etching apparatus, semiconductor devices and methods of fabricating semiconductor devices
04/21/2005US20050085088 Method and device for cutting wire formed on semiconductor substrate
04/21/2005US20050085087 Plasma processing method, plasma etching method and manufacturing method of solid-state image sensor
04/21/2005US20050085086 Contact plug processing and a contact plug
04/21/2005US20050085085 Composite patterning with trenches
04/21/2005US20050085084 Method of fabricating copper metallization on backside of gallium arsenide devices
04/21/2005US20050085083 Surface treated low-k dielectric as diffusion barrier for copper metallization
04/21/2005US20050085082 Method of forming a low k dielectric in a semiconductor manufacturing process
04/21/2005US20050085081 Process integration of SOI FETs with active layer spacer
04/21/2005US20050085080 Method of processing a semiconductor substrate
04/21/2005US20050085078 Light absorbent agent polymer useful for organic anti-reflective coating, its preparation method and organic anti-reflective coating composition comprising the same
04/21/2005US20050085077 Etching method
04/21/2005US20050085076 Inorganic compound for removing polymers in semiconductor processes
04/21/2005US20050085075 Method and apparatus for thermo-electric cooling
04/21/2005US20050085074 Selective oxidation methods and transistor fabrication methods
04/21/2005US20050085073 Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition
04/21/2005US20050085072 Formation of self-aligned contact plugs
04/21/2005US20050085071 Methods of forming conductive metal silicides by reaction of metal with silicon
04/21/2005US20050085070 Method for forming metal interconnection line in semiconductor device
04/21/2005US20050085069 Dual damascene partial gap fill polymer fabrication process
04/21/2005US20050085068 Method of depositing a metal seed layer on semiconductor substrates
04/21/2005US20050085066 Novel method to reduce Rs pattern dependence effect
04/21/2005US20050085064 Sacrificial metal spacer damascene process
04/21/2005US20050085063 Method for forming metal contacts on a substrate
04/21/2005US20050085062 Processes and tools for forming lead-free alloy solder precursors
04/21/2005US20050085061 Method of forming bumps
04/21/2005US20050085060 Self-aligned silicide process for preventing electrical shorts
04/21/2005US20050085059 Method for manufacturing word line of semiconductor device
04/21/2005US20050085058 Methods of forming conductive metal silicides by reaction of metal with silicon
04/21/2005US20050085057 Gas heating method and gas heating device
04/21/2005US20050085056 Integrated circuit with protected implantation profiles and method for the formation thereof
04/21/2005US20050085055 End of range (EOR) secondary defect engineering using substitutional carbon doping
04/21/2005US20050085054 Deposition of carbon and nitrogen doped poly silicon films, and retarded boron diffusion and improved poly depletion
04/21/2005US20050085052 Device having a getter
04/21/2005US20050085051 Tunable dielectric device and process relating thereto
04/21/2005US20050085050 Substrate thinning including planarization
04/21/2005US20050085049 Wafer bonded virtual substrate and method for forming the same
04/21/2005US20050085048 Method of fabricating shallow trench isolation with improved smiling effect
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