Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
04/2005
04/14/2005WO2005034209A2 Thin buried oxides by low-dose oxygen implantation into modified silicon
04/14/2005WO2005034208A2 METHOD TO REDUCE STACKING FAULT NUCLEATION SITES AND REDUCE Vf DRIFT IN BIPOLAR DEVICES
04/14/2005WO2005034207A2 Varying carrier mobility on finfet active surfaces to achieve overall design goals
04/14/2005WO2005034203A2 Method and apparatus for a dual substrate package
04/14/2005WO2005034202A2 Precision polysilicon resistor process
04/14/2005WO2005034201A2 Metal-insulator-metal capacitor and method of fabrication
04/14/2005WO2005034200A2 Adjustable self-aligned air gap dielectric for low capacitance wiring
04/14/2005WO2005034195A2 Growth of high-k dielectrics by atomic layer deposition
04/14/2005WO2005034194A2 Repairing damage to low-k dielectric materials using silylating agents
04/14/2005WO2005034187A2 Monitoring system comprising infrared thermopile detector
04/14/2005WO2005034186A2 Method for forming a semiconductor device having isolation regions
04/14/2005WO2005034185A2 System and method for on-tool semiconductor simulation
04/14/2005WO2005034178A2 A low profile carrier for non-wafer form device testing
04/14/2005WO2005034173A2 Standard tray carrier for aligning trays
04/14/2005WO2005034033A1 Characteristic value estimation method, device used for executing the estimation method, and processing program for executing the estimation method
04/14/2005WO2005033984A1 Net list conversion method, net list conversion device, still-state leak current detection method, and still-state leak current detection device
04/14/2005WO2005033801A2 Adaptive thermal control of lithographic chemical processes
04/14/2005WO2005033720A2 Testing apparatus and method for determining an etch bias associated with a semiconductor-processing step
04/14/2005WO2005033376A2 Plating method and apparatus
04/14/2005WO2005033375A2 Electrochemical fabrication methods with enhanced post deposition processing
04/14/2005WO2005033361A1 Gas distribution showerhead
04/14/2005WO2005033357A2 Low-pressure deposition of metal layers from metal-carbonyl precursors
04/14/2005WO2005033352A2 Deposition and patterning process
04/14/2005WO2005033234A2 Novel slurry for chemical mechanical polishing of metals
04/14/2005WO2005020319A3 Method for ltcc zero x-y shrinkage
04/14/2005WO2005015623A3 Reduction of defects in conductive layers during electroplating
04/14/2005WO2005013371A3 Semiconductor device including band-engineered superlattice
04/14/2005WO2005010981A3 Array of nanoscopic mosfet transistors and fabrication
04/14/2005WO2005000568A3 Lead frame device with vented die flag
04/14/2005WO2004109772A3 Method and system for etching a high-k dielectric material
04/14/2005WO2004107445B1 Method for fabricating a self-aligned bipolar transistor with planarizing layer and related structure
04/14/2005WO2004107394A3 Plasma processing apparatus, method for producing reaction vessel for plasma generation, and plasma processing method
04/14/2005WO2004107387A3 Apparatus and methods for compensating plasma sheath non-uniformities at the substrate in a plasma processing system
04/14/2005WO2004105098A3 P-type group ii-vi semiconductor compounds
04/14/2005WO2004104698A3 Dielectric materials to prevent photoresist poisoning
04/14/2005WO2004093151B1 Tray carrier with ultraphobic surfaces
04/14/2005WO2004093142A3 Light emitting device methods
04/14/2005WO2004092623A3 Fluid handling component with ultraphobic surfaces
04/14/2005WO2004090965A3 Organosilicate resin formulation for use in microelectronic devices
04/14/2005WO2004086461A3 Methods for nanoscale structures from optical lithography and subsequent lateral growth
04/14/2005WO2004074168A3 Packaged microchip with thermal stress relief
04/14/2005WO2004061903A3 Method for fabrication of semiconductor device
04/14/2005WO2004059697A3 Adaptive negative differential resistance device
04/14/2005US20050081180 Elicits an immune response against a canine IL-4 protein or has IL-4 activity.
04/14/2005US20050081176 Semiconductor device, routing method and manufacturing method of semiconductor device
04/14/2005US20050081171 Timing analysis apparatus, timing analysis method and program product
04/14/2005US20050081168 Multiple gate electrode linewidth monitor method
04/14/2005US20050080572 Method of defect control
04/14/2005US20050080508 Board positioning device and board positioning method
04/14/2005US20050080506 Method of determining remaining film thickness in polishing process
04/14/2005US20050080214 Multi-functional cyclic silicate compound, siloxane-based polymer prepared from the compound and process of producing insulating film using the polymer
04/14/2005US20050079851 Module integration integrated circuits
04/14/2005US20050079804 Planarizing solutions including abrasive elements, and methods for manufacturing and using such planarizing solutions
04/14/2005US20050079803 Chemical-mechanical planarization composition having PVNO and associated method for use
04/14/2005US20050079737 Mems based contact conductivity electrostatic chuck
04/14/2005US20050079736 Fabrication method for polycrystalline silicon thin film and display device fabricated using the same
04/14/2005US20050079735 Substrate for electronic device, method for manufacturing substrate for electronic device, and electronic device
04/14/2005US20050079734 Methods for fabricating an interlayer dielectric layer of a semiconductor device
04/14/2005US20050079733 Masking without photolithography during the formation of a semiconductor device
04/14/2005US20050079732 Method and device to form high quality oxide layers of different thickness in one processing step
04/14/2005US20050079731 Plasma enhanced chemical vapor deposition methods and semiconductor processing methods of forming layers and shallow trench isolation regions
04/14/2005US20050079730 Trench isolation employing a high aspect ratio trench
04/14/2005US20050079729 High density plasma oxide film deposition apparatus having a guide ring and a semiconductor device manufacturing method using the same
04/14/2005US20050079728 Method of reducing the surface roughness of spin coated polymer films
04/14/2005US20050079727 One mask PT/PCMO/PT stack etching process for RRAM applications
04/14/2005US20050079726 Self-aligned mask formed utilizing differential oxidation rates of materials
04/14/2005US20050079725 Selective oxygen-free etching process for barrier materials
04/14/2005US20050079724 Method for deep trench etching through a buried insulator layer
04/14/2005US20050079723 Method for removal of hydrocarbon contamination on gate oxide prior to non-thermal nitridation using "spike" radical oxidation
04/14/2005US20050079722 Methods of simultaneously fabricating isolation structures having varying dimensions
04/14/2005US20050079721 Vertically wired integrated circuit and method of fabrication
04/14/2005US20050079720 Substrate processing method and a computer readable storage medium storing a program for controlling same
04/14/2005US20050079719 Interconnect structures with engineered dielectrics with nanocolumnar porosity
04/14/2005US20050079718 Chemical-mechanical planarization composition with nitrogen containing polymer and method for use
04/14/2005US20050079717 Systems and methods for photoresist strip and residue treatment in integrated circuit manufacturing
04/14/2005US20050079716 Semiconductor optical device and method for manufacturing the same
04/14/2005US20050079715 Method for high aspect ratio HDP CVD gapfill
04/14/2005US20050079714 Method of etching silicon anisotropically
04/14/2005US20050079713 Edge and bevel cleaning process and system
04/14/2005US20050079712 Method for low temperature bonding and bonded structure
04/14/2005US20050079710 Nitrous oxide stripping process for organosilicate glass
04/14/2005US20050079709 Planarization system and method using a carbonate containing fluid
04/14/2005US20050079708 Method of depositing metal layers from metal-carbonyl precursors
04/14/2005US20050079706 Dual damascene structure and method
04/14/2005US20050079705 Process for producing semiconductor device and semiconductor device
04/14/2005US20050079704 Etch back process using nitrous oxide
04/14/2005US20050079703 Method for planarizing an interconnect structure
04/14/2005US20050079702 Method for producing an electrically conductive contact
04/14/2005US20050079701 Method for forming damascene structure utilizing planarizing material coupled with compressive diffusion barrier material
04/14/2005US20050079700 Strip conductor arrangement and method for producing a strip conductor arrangement
04/14/2005US20050079699 Oxidation method for semiconductor process
04/14/2005US20050079698 Contact structure and manufacturing method thereof
04/14/2005US20050079697 Plasma enhanced chemical vapor deposition method of forming a titanium silicide comprising layer
04/14/2005US20050079696 Encapsulated MOS transistor gate structures and methods for making the same
04/14/2005US20050079695 Process for fabricating a transistor with a metal gate, and corresponding transistor
04/14/2005US20050079694 Ion implantation method and method for manufacturing semiconductor device
04/14/2005US20050079693 Mask for crystallizing polysilicon and a method for forming thin film transistor using the mask
04/14/2005US20050079692 Methods to fabricate MOSFET devices using selective deposition process
04/14/2005US20050079691 Methods of selective deposition of heavily doped epitaxial SiGe
04/14/2005US20050079690 Method for producing silicon epitaxial wafer
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