Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2005
05/03/2005US6889162 Wafer target design and method for determining centroid of wafer target
05/03/2005US6889149 System and method for fingerprinting of semiconductor processing tools
05/03/2005US6889108 Processing system and processing method
05/03/2005US6889105 Scheduling method and program for a substrate processing apparatus
05/03/2005US6889014 Exposure system, device production method, semiconductor production factory, and exposure apparatus maintenance method
05/03/2005US6889004 Thermal processing system and thermal processing method
05/03/2005US6888959 Method of inspecting a semiconductor device and an apparatus thereof
05/03/2005US6888921 Laser plasma X-ray generating apparatus
05/03/2005US6888865 Semiconductor laser apparatus and method of producing the same
05/03/2005US6888773 Semiconductor memory device and erase method for memory array
05/03/2005US6888770 Semiconductor memory device
05/03/2005US6888766 Semiconductor memory device provided with test memory cell unit
05/03/2005US6888759 Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch
05/03/2005US6888755 Flash memory cell arrays having dual control gates per memory cell charge storage element
05/03/2005US6888753 Memory cell array comprising individually addressable memory cells and method of making the same
05/03/2005US6888751 Nonvolatile semiconductor memory device
05/03/2005US6888750 Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication
05/03/2005US6888749 P-channel dynamic flash memory cells with ultrathin tunnel oxides
05/03/2005US6888747 Methods of reading junction-isolated depletion mode ferroelectric memory devices
05/03/2005US6888740 Two-transistor SRAM cells
05/03/2005US6888738 Methods of writing junction-isolated depletion mode ferroelectric memory devices
05/03/2005US6888735 Ferroelectric-type nonvolatile semiconductor memory
05/03/2005US6888716 On-die de-coupling capacitor using bumps or bars
05/03/2005US6888714 Tuneable ferroelectric decoupling capacitor
05/03/2005US6888639 In-situ film thickness measurement using spectral interference at grazing incidence
05/03/2005US6888619 Positioning device
05/03/2005US6888618 Exposure apparatus and exposure method
05/03/2005US6888617 Reversed, double-helical bellows seal
05/03/2005US6888616 Programmable photolithographic mask system and method
05/03/2005US6888615 System and method for improving linewidth control in a lithography device by varying the angular distribution of light in an illuminator as a function of field position
05/03/2005US6888587 Liquid crystal displays
05/03/2005US6888520 Active matrix type display
05/03/2005US6888414 Controllable and testable oscillator apparatus for an integrated circuit
05/03/2005US6888397 Temperature sensor circuit, semiconductor integrated circuit, and method of adjusting the temperature sensor circuit
05/03/2005US6888395 Semiconductor integrated circuit device
05/03/2005US6888378 Semiconductor integrated circuit
05/03/2005US6888368 System and method of monitoring, predicting and optimizing production yields in a liquid crystal display (LCD) manufacturing process
05/03/2005US6888366 Apparatus and method for testing a plurality of semiconductor chips
05/03/2005US6888317 Organic electroluminescent device
05/03/2005US6888261 Alignment mark and exposure alignment system and method using the same
05/03/2005US6888258 Adhesion between a pad area and a wire; simplification
05/03/2005US6888257 Useful for integrated circuit packages enabling conducting heat generated by the die
05/03/2005US6888256 Compliant relief wafer level packaging
05/03/2005US6888254 Semiconductor device
05/03/2005US6888252 Method of forming a conductive contact
05/03/2005US6888251 Metal spacer in single and dual damascene processing
05/03/2005US6888250 Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium
05/03/2005US6888249 Fabrication of semiconductor devices with air gaps for ultra low capacitance interconnections and methods of making same
05/03/2005US6888247 Interconnect structure with an enlarged air gaps disposed between conductive structures or surrounding a conductive structure within the same
05/03/2005US6888246 Semiconductor power device with shear stress compensation
05/03/2005US6888245 Semiconductor device
05/03/2005US6888244 Interconnect arrangement and method for fabricating an interconnect arrangement
05/03/2005US6888243 Semiconductor device
05/03/2005US6888242 Color contacts for a semiconductor package
05/03/2005US6888239 Ceramic package sealing structure and ceramic package having said sealing structure
05/03/2005US6888237 Encapsulation of a device
05/03/2005US6888234 Semiconductor device and manufacturing method for the same
05/03/2005US6888232 Semiconductor package having a heat-activated source of releasable hydrogen
05/03/2005US6888231 Surface mounting semiconductor device
05/03/2005US6888230 Semiconductor device, semiconductor wafer, semiconductor module, and a method of manufacturing semiconductor device
05/03/2005US6888229 Connection components with frangible leads and bus
05/03/2005US6888228 Lead frame chip scale package
05/03/2005US6888225 Process of final passivation of an integrated circuit device
05/03/2005US6888224 Methods and systems for fabricating electrical connections to semiconductor structures incorporating low-k dielectric materials
05/03/2005US6888223 Use of photoresist in substrate vias during backside grind
05/03/2005US6888222 Semiconductor device
05/03/2005US6888221 BICMOS technology on SIMOX wafers
05/03/2005US6888220 Semiconductor device having a buried wiring lead structure
05/03/2005US6888219 Integrated structure with microwave components
05/03/2005US6888217 Capacitor for use in an integrated circuit
05/03/2005US6888216 Circuit having make-link type fuse and semiconductor device having the same
05/03/2005US6888215 Dual damascene anti-fuse with via before wire
05/03/2005US6888214 Isolation techniques for reducing dark current in CMOS image sensors
05/03/2005US6888213 Dielectric insulation structure for integrating electronic semiconductor devices and relevant manufacturing process
05/03/2005US6888212 Method for trench isolation by selective deposition of low temperature oxide films
05/03/2005US6888210 Lateral DMOS transistor having reduced surface field
05/03/2005US6888207 High voltage transistors with graded extension
05/03/2005US6888205 Metal oxide semiconductor field-effect transistor having a gate oxide layer with portions of different thicknesses and associated methods
05/03/2005US6888204 Semiconductor devices, and methods for same
05/03/2005US6888201 Bipolar ESD protection structure
05/03/2005US6888199 High-density split-gate FinFET
05/03/2005US6888198 Straddled gate FDSOI device
05/03/2005US6888196 Vertical MOSFET reduced in cell size and method of producing the same
05/03/2005US6888195 Semiconductor device with alternating conductivity type layers having different vertical impurity concentration profiles
05/03/2005US6888194 Nonvolatile semiconductor memory device, manufacturing method thereof, and operating method thereof
05/03/2005US6888193 Split gate flash memory and formation method thereof
05/03/2005US6888192 Mirror image non-volatile memory cell transistor pairs with single poly layer
05/03/2005US6888191 Semiconductor device and fabrication process therefor
05/03/2005US6888190 EEPROM with source line voltage stabilization mechanism
05/03/2005US6888189 Dielectric element including oxide-based dielectric film and method of fabricating the same
05/03/2005US6888188 Capacitor constructions comprising perovskite-type dielectric materials and having different degrees of crystallinity within the perovskite-type dielectric materials
05/03/2005US6888187 DRAM cell with enhanced SER immunity
05/03/2005US6888186 Reduction of damage in semiconductor container capacitors
05/03/2005US6888185 Junction-isolated depletion mode ferroelectric memory devices
05/03/2005US6888184 Shielded magnetic ram cells
05/03/2005US6888183 Manufacture method for semiconductor device with small variation in MOS threshold voltage
05/03/2005US6888182 Thin film transistor, method for manufacturing same, and liquid crystal display device using same
05/03/2005US6888181 Triple gate device having strained-silicon channel
05/03/2005US6888180 Hetero-junction bipolar transistor and a method for manufacturing the same
05/03/2005US6888179 GaAs substrate with Sb buffering for high in devices
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