Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2005
07/14/2005US20050151274 Semiconductor memory device and fabrication method thereof using damascene gate and epitaxial growth
07/14/2005US20050151273 integrated circuit chip, a chip contact pad, a stud, a substrate, and a support member
07/14/2005US20050151271 comprising: curing agent to generate free radicals with heating; a radically polymerizable substance; and film-forming polymer, wherein a temporary fixing power to a flexible substrate having the circuit electrode is 40-180 N/m
07/14/2005US20050151270 Materials for electronic devices
07/14/2005US20050151269 UBM for fine pitch solder balland flip-chip packaging method using the same
07/14/2005US20050151266 Semiconductor device and method of manufacturing the same
07/14/2005US20050151264 Fabrication process for a semiconductor integrated circuit device
07/14/2005US20050151263 Wiring structure forming method and semiconductor device
07/14/2005US20050151262 Semiconductor integrated circuit device
07/14/2005US20050151261 Ultra-high capacitance device based on nanostructures
07/14/2005US20050151260 forming a plurality of lower patterns each comprising a first lower metal pattern and a capping pattern; sequentially stacked; photolithography
07/14/2005US20050151259 Semiconductor device and manufacturing method thereof
07/14/2005US20050151257 Semiconductor device and method of manufacturing the same
07/14/2005US20050151255 Semiconductor device having schottky junction electrode
07/14/2005US20050151254 Semiconductor device
07/14/2005US20050151251 Mounting substrate and electronic component using the same
07/14/2005US20050151250 Semiconductor device and manufacturing method thereof
07/14/2005US20050151246 Multilayer circuit carrier, panel, electronic device, and method for producing a multilayer circuit carrier
07/14/2005US20050151239 Integrated circuit devices, edge seals therefor
07/14/2005US20050151237 Multi-chip assembly and method for driving the same
07/14/2005US20050151235 Semiconductor device and manufacturing method for the same
07/14/2005US20050151233 Conductive material compositions, apparatus, systems, and methods
07/14/2005US20050151232 Methods of treating a silicon carbide substrate for improved epitaxial deposition and resulting structures and devices
07/14/2005US20050151228 Semiconductor chip and manufacturing method for the same, and semiconductor device
07/14/2005US20050151227 Novel EBR shape of spin-on low-k material providing good film stacking
07/14/2005US20050151225 Bipolar transistor structure with self-aligned raised extrinsic base and methods
07/14/2005US20050151224 Semiconductor device and manufacturing method thereof
07/14/2005US20050151223 Tunable semiconductor diodes
07/14/2005US20050151222 Shallow trench isolation process and structure with minimized strained silicon consumption
07/14/2005US20050151221 Semiconductor substrate and semiconductor device using the same
07/14/2005US20050151220 Semiconductor device and cell
07/14/2005US20050151219 Diode and method for manufacturing the same
07/14/2005US20050151218 Using high-k dielectrics in isolation structures method, pixel and imager device
07/14/2005US20050151217 Integrated circuit device packaging structure and packaging method
07/14/2005US20050151216 Integrated circuit device packaging structure and packaging method
07/14/2005US20050151213 Method and structure for integrating thermistor
07/14/2005US20050151211 Semiconductor device, and method and apparatus for manufacturing the same
07/14/2005US20050151210 In2O3 thin film resistivity control by doping metal oxide insulator for MFMox device applications
07/14/2005US20050151209 Semiconductor device including p-channel type transistor, and production method for manufacturing such semiconductor device
07/14/2005US20050151207 Metal oxide semiconductor field-effect transistor and associated methods
07/14/2005US20050151206 Transistor structure with a curved channel, memory cell and memory cell array for DRAMs, and methods for fabricating a DRAM
07/14/2005US20050151205 Nonvolatile semiconductor memory device
07/14/2005US20050151203 Temporary self-aligned stop layer is applied on silicon sidewall
07/14/2005US20050151202 Semiconductor device having a retrograde dopant profile in a channel region
07/14/2005US20050151201 Process for production of SOI substrate and process for production of semiconductor device
07/14/2005US20050151199 Polysilicon thin film transistor and method of forming the same
07/14/2005US20050151198 Apparatus for increasing SRAM cell capacitance with metal fill
07/14/2005US20050151197 Production method of flexible electronic device
07/14/2005US20050151196 Polysilicon thin film transistor array panel and manufacturing method thereof
07/14/2005US20050151195 Method of manufacturing a thin film transistor, thin film transistor, thin film transistor circuit, electronic device, and electronic apparatus
07/14/2005US20050151194 Method of forming thin-film transistor devices with electro-static discharge protection
07/14/2005US20050151192 Reduction of chemical mechanical planarization (CMP) scratches with sacrificial dielectric polish stop
07/14/2005US20050151191 Semiconductor device and method of manufacturing the same
07/14/2005US20050151190 Power transistor arrangement and method for fabricating it
07/14/2005US20050151189 Shrunk low on-resistance DMOS structure
07/14/2005US20050151188 Semiconductor device and manufacturing method thereof
07/14/2005US20050151185 Semiconductor device and fabricating method thereof
07/14/2005US20050151184 Dielectric layer for semiconductor device and method of manufacturing the same
07/14/2005US20050151183 Novel random access memory (RAM) capacitor in shallow trench isolation with improved electrical isolation to overlying gate electrodes
07/14/2005US20050151182 Isolation structure for trench capacitors and fabrication method thereof
07/14/2005US20050151181 Nitrided sti liner oxide for reduced corner device impact on vertical device performance
07/14/2005US20050151180 Method to reduce a capacitor depletion phenomena
07/14/2005US20050151179 Dopant barrier for doped glass in memory devices
07/14/2005US20050151178 Buried collar trench capacitor formed by LOCOS using self starved ALD nitride as an oxidation mask
07/14/2005US20050151177 Ferroelectric film, ferroelectric capacitor, and ferroelectric memory
07/14/2005US20050151176 Memory cell
07/14/2005US20050151174 Semiconductor device and fabricating method thereof
07/14/2005US20050151173 Semiconductor device and methods of manufacturing the same
07/14/2005US20050151172 Semiconductor device and its manufacturing method
07/14/2005US20050151171 JFET structure for integrated circuit and fabrication method
07/14/2005US20050151168 Semiconductor device and method of manufacturing the same
07/14/2005US20050151166 Metal contact structure and method of manufacture
07/14/2005US20050151165 Structure and method of making heterojunction bipolar transistor having self-aligned silicon-germanium raised extrinsic base
07/14/2005US20050151164 Enhancement of p-type metal-oxide-semiconductor field effect transistors
07/14/2005US20050151163 Semiconductor device and manufacturing method thereof
07/14/2005US20050151158 Silicon carbide semiconductor device having junction field effect transistor and method for manufacturing the same
07/14/2005US20050151155 Method of fabricating substrates and substrates obtained by this method
07/14/2005US20050151150 Semiconductor laser diode and method of manufacturing the same
07/14/2005US20050151147 Semiconductor device and method for manufacturing the same
07/14/2005US20050151146 Crystallization mask, crystallization method, and method of manufacturing thin film transistor including crystallized semiconductor
07/14/2005US20050151138 Methods of processing semiconductor wafer backsides having light emitting devices (LEDS) thereon and leds so formed
07/14/2005US20050151136 Light emitting diode having conductive substrate and transparent emitting surface
07/14/2005US20050151134 Method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications
07/14/2005US20050151133 SOI semiconductor device having enhanced, self-aligned dielectric regions in the bulk silicon substrate
07/14/2005US20050151132 Semiconductor device and method of manufacturing the same
07/14/2005US20050151131 Polycrystalline thin-film solar cells
07/14/2005US20050151130 Electronic devices containing organic semiconductor materials
07/14/2005US20050151127 Variable resistance functional body, manufacturing method therefor and storage device
07/14/2005US20050151096 Lithographic apparatus and device manufacturing method
07/14/2005US20050151095 Reflection element of exposure light and production method therefor, mask, exposure system, and production method of semiconductor device
07/14/2005US20050151089 Manipulator assembly in ion implanter
07/14/2005US20050151088 comprises cadmium/tellurium intermetallic arranged in two-dimensional matrix, mounted to integrated circuit substrate via laminated connection layer with stud bumps
07/14/2005US20050151078 Method for determining depression/protrusion of sample and charged particle beam apparatus therefor
07/14/2005US20050151077 Scanning probe microscope and specimen observation method and semiconductor device manufacturing method using said scanning probe microscope
07/14/2005US20050151062 Semiconductor device, optoelectronic board, and production methods therefor
07/14/2005US20050150936 Bumping electronic components using transfer substrates
07/14/2005US20050150933 System and method for increasing the strength of a bond made by a small diameter wire in ball bonding
07/14/2005US20050150880 Laser-based method and system for memory link processing with picosecond lasers
07/14/2005US20050150879 Laser-based method and system for memory link processing with picosecond lasers
07/14/2005US20050150877 Method and device for laser beam processing of silicon substrate, and method and device for laser beam cutting of silicon wiring