Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2005
07/14/2005WO2005029547A3 Enhancing the width of polycrystalline grains with mask
07/14/2005WO2005024930A3 Method for producing a semiconductor component with a praseodymium oxide dielectric
07/14/2005WO2005017949A3 Method for high-resolution processing of thin layers with electron beams
07/14/2005WO2005008763B1 Methods of forming deuterated silicon nitride-containing materials
07/14/2005WO2004112128A3 Low profile stacking system and method
07/14/2005WO2004112077A3 Rf current return path for a large area substrate plasma reactor
07/14/2005WO2004109773A3 Method and system for heating a substrate using a plasma
07/14/2005WO2004107409A3 Method for fabricating a self-aligned bipolar transistor having increased manufacturabily and related structure
07/14/2005WO2004106986A3 Maskless fabrication of waveguide mirrors
07/14/2005WO2004101856A3 Methods for electrochemically fabricating structures using adhered masks, incorporating dielectric sheets, and/or seed layers that are partially removed via planarization
07/14/2005WO2004094548A3 Adhesive of a silicon and silica composite particularly useful for joining silicon parts
07/14/2005WO2004081261B1 Plating apparatus
07/14/2005WO2004079784A3 Integrated photodetector and heterojunction bipolar transistors
07/14/2005WO2004055882A8 Method of manufacturing a trench-gate semiconductor device
07/14/2005WO2004049398B1 Porogen material
07/14/2005WO2004046099A3 Method of making a molecule-surface interface
07/14/2005WO2004020969A3 Production of nanoparticles having a defined number of ligands
07/14/2005WO2004017373A3 Complementary analog bipolar transistors with trench-constrained isolation diffusion
07/14/2005WO2003067655A9 Method and structure for forming an hbt
07/14/2005US20050155009 Cell based integrated circuit and unit cell architecture therefor
07/14/2005US20050155007 Automatic layout method of semiconductor integrated circuit
07/14/2005US20050155004 Simulation model for design of semiconductor device, thermal drain noise analysis method, simulation method, and simulation apparatus
07/14/2005US20050155001 Method for designing a semiconductor integrated circuit and a semiconductor integrated circuit
07/14/2005US20050154567 Three-dimensional microstructures
07/14/2005US20050154482 Plasma processing method and apparatus
07/14/2005US20050154077 Reacting a polymer such as a polyether sulfone or a polyether carbonyl that has haloalkyl substituents with an allyl alcoholate or an allylphenolate; the allyl ether groups formed can be reacted with a peroxide to form epoxy groups that can be crosslinked; used for thermal ink jet print heads
07/14/2005US20050153826 Carbon-containing aluminum nitride sintered body, and ceramic substrate for a semiconductor producing/examining device
07/14/2005US20050153643 Polyelectrolyte dispensing polishing pad
07/14/2005US20050153633 Polishing pad, polishing apparatus, and polishing method
07/14/2005US20050153575 Semiconductor device with analog capacitor and method of fabricating the same
07/14/2005US20050153574 Very low dielectric constant plasma-enhanced CVD films
07/14/2005US20050153573 Semiconductor device and manufacturing method thereof
07/14/2005US20050153572 CVD plasma assisted lower dielectric constant sicoh film
07/14/2005US20050153571 Nitridation of high-k dielectric films
07/14/2005US20050153570 Substrate processing method
07/14/2005US20050153569 Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3
07/14/2005US20050153568 Method for removing mottled etch in semiconductor fabricating process
07/14/2005US20050153567 Method of forming patterns
07/14/2005US20050153566 Method of fabricating microelectronic device using super critical fluid
07/14/2005US20050153565 Methods of manufacturing semiconductor devices
07/14/2005US20050153564 Integrated phase angle and optical critical dimension measurement metrology for feed forward and feedback process control
07/14/2005US20050153563 Selective etch of films with high dielectric constant
07/14/2005US20050153562 Method of independent P and N gate length control of FET device made by sidewall image transfer technique
07/14/2005US20050153561 Chemical mechanical polishing a substrate having a filler layer and a stop layer
07/14/2005US20050153560 Performing first and second polishing steps, polishing mixtures used in first and second steps include ceria abrasives of different grain concentrations; polishing rate being changed between steps; dishing is prevented
07/14/2005US20050153557 Apparatus and method for treating susbtrates
07/14/2005US20050153556 Methods for polishing copper features of semiconductor devices structures
07/14/2005US20050153555 Method for chemical mechanical polishing of a shallow trench isolation structure
07/14/2005US20050153554 Integrated polishing and electroless deposition
07/14/2005US20050153553 Etching method
07/14/2005US20050153552 Crystallization apparatus and method, manufacturing method of electronic device, electronic device, and optical modulation element
07/14/2005US20050153551 Methods for deposition of semiconductor material
07/14/2005US20050153550 Process for producing silicon single crystal layer and silicon single crystal layer
07/14/2005US20050153549 Method of forming metal wiring for high voltage element
07/14/2005US20050153548 Method for fabricating semiconductor device to minimize terminal effect in ECP process
07/14/2005US20050153547 Method and apparatus for selective deposition
07/14/2005US20050153546 Method for fabrication of a contact structure
07/14/2005US20050153545 Methods of forming copper interconnections using electrochemical plating processes
07/14/2005US20050153544 Method of fabricating semiconductor device by forming diffusion barrier layer selectively and semiconductor device fabricated thereby
07/14/2005US20050153543 Method of forming self aligned contact
07/14/2005US20050153542 Method for forming dual damascene pattern
07/14/2005US20050153541 Method of forming metal wiring in a semiconductor device
07/14/2005US20050153540 Method of forming contact hole and method of manufacturing semiconductor device
07/14/2005US20050153539 Method of forming interconnection lines in a semiconductor device
07/14/2005US20050153538 Method for forming novel BARC open for precision critical dimension control
07/14/2005US20050153537 Novel nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure
07/14/2005US20050153536 Method for manufacturing semiconductor device
07/14/2005US20050153535 Method for forming contact in semiconductor device
07/14/2005US20050153534 Electric contacts and method of manufacturing thereof, and vacuum interrupter and vacuum circuit breaker using thereof
07/14/2005US20050153533 Semiconductor manufacturing method and semiconductor manufacturing apparatus
07/14/2005US20050153532 Methods and apparatus to reduce growth formations on plated conductive leads
07/14/2005US20050153531 Method of fabricating gate electrode of semiconductor device
07/14/2005US20050153530 Fet gate structure with metal gate electrode and silicide contact
07/14/2005US20050153529 Semiconductor devices and methods for fabricating the same
07/14/2005US20050153528 Method for manufacturing a semiconductor device having a low junction leakage current
07/14/2005US20050153527 Method of manufacturing semiconductor device
07/14/2005US20050153526 Method for manufacturing a semiconductor device having a low junction leakage current
07/14/2005US20050153525 Method and apparatus for cutting devices from substrates
07/14/2005US20050153524 Strained silicon on insulator from film transfer and relaxation by hydrogen implantation
07/14/2005US20050153522 Wafer level chip stack method
07/14/2005US20050153521 Method of manufacturing a semiconductor device
07/14/2005US20050153520 Method for manufacturing semiconductor device
07/14/2005US20050153519 Novel shallow trench isolation method for reducing oxide thickness variations at different pattern densities
07/14/2005US20050153518 Method for forming capacitor using etching stopper film in semiconductor memory
07/14/2005US20050153517 Modifying U-shaped window spacers to receive internal blinds or other hardware
07/14/2005US20050153516 Method for etching upper metal of capacitator
07/14/2005US20050153514 Method of manufacturing dielectric layer in non-volatile memory cell
07/14/2005US20050153513 Method of forming a dielectric layer for a non-volatile memory cell and method of forming a non-volatile memory cell having the dielectric layer
07/14/2005US20050153512 Method of forming an EPROM cell and structure therefor
07/14/2005US20050153511 Methods of fabricating nonvolatile memory device
07/14/2005US20050153510 Etch stop layer in poly-metal structures
07/14/2005US20050153509 Method for manufacturing flash memory cell
07/14/2005US20050153508 Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell
07/14/2005US20050153507 Fabrication method for a trench capacitor with an insulation collar
07/14/2005US20050153506 Isolation structure for trench capacitors and fabrication method thereof
07/14/2005US20050153505 Sacrificial inorganic polymer intermetal dielectric damascene wire and via liner
07/14/2005US20050153504 Method for manufacturing nonvolatile semiconductor memory device
07/14/2005US20050153503 Method of manufacturing flash memory device
07/14/2005US20050153502 Flash memory device and method of manufacturing the same
07/14/2005US20050153501 Method for fabricating image sensor
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