Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2005
08/18/2005WO2005076335A1 Composite shape electro-forming member, its electro-forming master and method for manufacturing the same
08/18/2005WO2005076334A1 Electro-forming master and the same-master-manufacturing method, and metal minute pattern made by the master
08/18/2005WO2005076333A1 Method for manufacturing semiconductor wafer and system for determining cut position of semiconductor ingot
08/18/2005WO2005076332A1 Substrate cleaning liquid for semiconductor device and cleaning method
08/18/2005WO2005076331A1 Method of fabricating metal-oxide semiconductor integrated circuit devices.
08/18/2005WO2005076330A1 Transistor with doped gate dielectric
08/18/2005WO2005076329A1 Ion doping apparatus, ion doping method, semiconductor device, and method of fabricating semiconductor device
08/18/2005WO2005076328A1 Method for introducing impurities
08/18/2005WO2005076327A1 Silicon carbide semiconductor device and process for producing the same
08/18/2005WO2005076326A1 Method for manufacturing semiconductor device
08/18/2005WO2005076325A1 Exposure equipment and method, position control method and device manufacturing method
08/18/2005WO2005076324A1 Exposure apparatus, exposure method, and device producing method
08/18/2005WO2005076323A1 Aligner, device manufacturing method, maintenance method and aligning method
08/18/2005WO2005076322A1 Aligner and semiconductor device manufacturing method using the aligner
08/18/2005WO2005076321A1 Exposure apparatus and method of producing device
08/18/2005WO2005076320A1 Integrated circuit design method, design support program used in the integrated circuit design method, and integrated circuit design system
08/18/2005WO2005076281A1 Nonvolatile memory
08/18/2005WO2005076202A1 Electronic device
08/18/2005WO2005076192A1 Method and apparatus for determining chemistry of part’s residual contamination
08/18/2005WO2005076165A1 Method of automatically generating the structures from mask layout
08/18/2005WO2005076076A2 Directly photodefinable polymer compositions and methods thereof
08/18/2005WO2005076045A1 Polarization conversion element, lighting optical device, exposure system, and exposure method
08/18/2005WO2005076039A1 Beam measuring equipment and beam measuring method using the same
08/18/2005WO2005075711A1 Method and composition for polishing a substrate
08/18/2005WO2005075701A1 Thin film forming apparatus
08/18/2005WO2005075339A2 Novel nanostructures and method for selective preparation
08/18/2005WO2005075118A1 Cleaning device of board and cleaning method, flat display panel, mounting equipment of electronic parts and mounting method
08/18/2005WO2005075014A1 Catheter tip
08/18/2005WO2005074659A2 Semiconductor device containing dielectrically isolated pn junction for enhanced breakdown characteristics
08/18/2005WO2005074578A2 Semiconductor devices, methods, and systems
08/18/2005WO2005074531A2 Methods of synthesis of isotopically enriched borohydride and methods of synthesis of isotopically enriched boranes
08/18/2005WO2005074471A2 Method for forming a memory structure using a modified surface topography and structure thereof
08/18/2005WO2005074451A2 Technique for perfecting the active regions of wide bandgap semiconductor nitride devices
08/18/2005WO2005074450A2 Substrate holder having a fluid gap and method of fabricating the substrate holder
08/18/2005WO2005074449A2 Structure comprising amorphous carbon film and method of forming thereof
08/18/2005WO2005067009A3 Process controls for improved wafer uniformity using integrated or standalone metrology
08/18/2005WO2005059978A3 Single-crystal semiconductor layer with heteroaromatic macro-network
08/18/2005WO2005059954A3 Method of forming a low voltage gate oxide layer and tunnel oxide layer in an eeprom cell
08/18/2005WO2005052988A3 Focused photon energy heating chamber
08/18/2005WO2005045902A3 Semiconductor device and manufacturing method thereof
08/18/2005WO2005038081A3 Substrate heater assembly
08/18/2005WO2005019497B1 Methods of reducing plasma-induced damage for advanced plasma cvd dielectrics
08/18/2005WO2005010947A3 Cleaning masks
08/18/2005WO2005008737A3 Inspection and metrology module cluster tool with multi-tool manager
08/18/2005WO2005004205A3 Methods for forming patterns of a filled dielectric material on substrates
08/18/2005WO2005000363A3 Atmospheric pressure non-thermal plasma device to clean and sterilize the surface of probes, cannulas, pin tools, pipettes and spray heads
08/18/2005WO2004111730A3 Developer composition for resists and method for formation of resist pattern
08/18/2005WO2004107398A3 Semiconductor device with an air gap formed using a photosensitive material
08/18/2005WO2004104708A3 Seal and support structure for semiconductor wafer
08/18/2005WO2004102633A3 Method for fabrication of sige layer having small poly grains and related structure
08/18/2005WO2004102307A3 Method and system for monitoring and control of a chamber process
08/18/2005WO2004095514A3 Circuit device with at least partial packaging and method for forming
08/18/2005WO2004088755A8 Nanowhiskers with pn junctions and methods of fabricating thereof
08/18/2005WO2004017371A3 Method for microfabricating structures using silicon-on-insulator material
08/18/2005WO2003095712A3 Method of and apparatus for forming three-dimensional structures integral with semiconductor based circuitry
08/18/2005WO2003095710A3 Methods of and apparatus for electrochemically fabricating structures
08/18/2005WO2003061354A3 System and methods for conveying and transporting levitated articles
08/18/2005WO2002031227A3 Deposition uniformity control for electroplating apparatus, and associated method
08/18/2005US20050183056 Simulator of lithography tool, simulation method, and computer program product for simulator
08/18/2005US20050183053 Software product for and method of laying-out semiconductor device
08/18/2005US20050183049 Method of generating capacitance value rule table for extraction of wiring capacitance and capacitance value rule table generation program
08/18/2005US20050182596 Method and system for analyzing wafer yield against uses of a semiconductor tool
08/18/2005US20050182593 Wafer target design and method for determining centroid of wafer target
08/18/2005US20050182587 Circuit quality evaluation method and apparatus, circuit quality evaluation program, and medium having the program recorded thereon
08/18/2005US20050182585 Structure and method for package burn-in testing
08/18/2005US20050182227 Composition for forming insulating film and process for producing insulating film
08/18/2005US20050182151 Low dielectric constant polyorganosilicon materials generated from polycarbosilanes
08/18/2005US20050181713 Water jet-processing machine
08/18/2005US20050181680 Semiconductor device
08/18/2005US20050181655 Micro pin grid array with wiping action
08/18/2005US20050181633 Precursors for depositing silicon-containing films and processes thereof
08/18/2005US20050181632 HDP-CVD deposition process for filling high aspect ratio gaps
08/18/2005US20050181631 Densifying a relatively porous material
08/18/2005US20050181630 Method of making a semiconductor device using treated photoresist
08/18/2005US20050181629 Fibrillar microstructure and processes for the production thereof
08/18/2005US20050181628 Process for preparing low dielectric constant material
08/18/2005US20050181626 Manufacture of semiconductor device having nitridized insulating film
08/18/2005US20050181625 Method for transistor gate dielectric layer with uniform nitrogen concentration
08/18/2005US20050181624 Method of forming quantum dots at predetermined positions on a substrate
08/18/2005US20050181623 Silicon carbide deposition for use as a low dielectric constant anti-reflective coating
08/18/2005US20050181622 Removing silicon nano-crystals
08/18/2005US20050181621 Methods of forming doped and un-doped strained semiconductor and semiconductor films by gas-cluster ion irradiation
08/18/2005US20050181620 Fluorinated surfactants for aqueous acid etch solutions
08/18/2005US20050181619 Method for forming metal oxide layer by nitric acid oxidation
08/18/2005US20050181618 Polymer via etching process
08/18/2005US20050181616 Dry etching process for compound semiconductors
08/18/2005US20050181615 Integrated circuit process monitoring and metrology system
08/18/2005US20050181613 Supercritical fluid-assisted deposition of materials on semiconductor substrates
08/18/2005US20050181612 Chemical thinning of silicon body of an SOI substrate
08/18/2005US20050181610 Method of manufacturing a semiconductor device
08/18/2005US20050181609 Polishing fluid and polishing method
08/18/2005US20050181608 Method and apparatus for etching photomasks
08/18/2005US20050181607 Method of manufacturing a semiconductor device
08/18/2005US20050181605 Method of manufacturing semiconductor device
08/18/2005US20050181604 Method for structuring metal by means of a carbon mask
08/18/2005US20050181603 Alloying method, and wiring forming method, display device forming method, and image display unit fabricating method
08/18/2005US20050181602 Alloying method, and wiring forming method, display device forming method, and image display unit fabricating method
08/18/2005US20050181601 Alloying method, and wiring forming method, display device forming method, and image display unit fabricating method
08/18/2005US20050181600 Method of forming a semiconductor device having a Ti/TiN/Ti<002>/a1<111> laminate
08/18/2005US20050181599 Methods of providing ohmic contact
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