Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
08/2005
08/16/2005US6930321 Robust electrode patterning in OLED devices
08/16/2005US6930319 Method for dense pixel fabrication and product thereof
08/16/2005US6930317 Charged particle beam apparatus, charged particle beam irradiation method, and method of manufacturing semiconductor device
08/16/2005US6930316 Ion implantation system and ion implantation method
08/16/2005US6930313 Emission source having carbon nanotube, electron microscope using this emission source, and electron beam drawing device
08/16/2005US6930276 Wafer cutting using laser marking
08/16/2005US6930257 Integrated circuit substrate having laminated laser-embedded circuit layers
08/16/2005US6930256 Integrated circuit substrate having laser-embedded conductive patterns and method therefor
08/16/2005US6930062 Methods of forming an oxide layer in a transistor having a recessed gate
08/16/2005US6930061 Plasma processes for depositing low dielectric constant films
08/16/2005US6930060 Method for forming a uniform distribution of nitrogen in silicon oxynitride gate dielectric
08/16/2005US6930059 Method for depositing a nanolaminate film by atomic layer deposition
08/16/2005US6930058 Method of depositing a silicon dioxide comprising layer doped with at least one of P, B and Ge
08/16/2005US6930056 Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for integrated circuit structure
08/16/2005US6930054 Slurry composition for use in chemical mechanical polishing of metal wiring
08/16/2005US6930052 Method for producing an integrated circuit having at least one metalicized surface
08/16/2005US6930051 Method to fabricate multi-level silicon-based microstructures via use of an etching delay layer
08/16/2005US6930050 Multi-chamber system having compact installation set-up for an etching facility for semiconductor device manufacturing
08/16/2005US6930049 Endpoint control for small open area by RF source parameter Vdc
08/16/2005US6930048 Etching a metal hard mask for an integrated circuit structure
08/16/2005US6930047 Dry etching apparatus, etching method, and method of forming a wiring
08/16/2005US6930046 Single workpiece processing system
08/16/2005US6930045 Cross reference to related application
08/16/2005US6930044 Method for fabricating a packaging substrate
08/16/2005US6930043 Method for forming DRAM cell bit line and bit line contact structure
08/16/2005US6930042 Method for producing a semiconductor component with at least one encapsulated chip on a substrate
08/16/2005US6930041 Photo-assisted method for semiconductor fabrication
08/16/2005US6930040 Method of forming a contact on a silicon-on-insulator wafer
08/16/2005US6930039 Method of fabricating a contact structure having a composite barrier layer between a platinum layer and a polysilicon plug
08/16/2005US6930038 Dual damascene partial gap fill polymer fabrication process
08/16/2005US6930037 Process for forming a metal interconnect
08/16/2005US6930036 Semiconductor device and method of manufacturing the same
08/16/2005US6930035 Semiconductor device fabrication method
08/16/2005US6930034 Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence
08/16/2005US6930033 Treating surface of low-dielectric constant material to achieve good mechanical strength
08/16/2005US6930032 Under bump metallurgy structural design for high reliability bumped packages
08/16/2005US6930031 Bumping process
08/16/2005US6930030 Method of forming an electronic device on a recess in the surface of a thin film of silicon etched to a precise thickness
08/16/2005US6930029 Method of passivating an oxide surface subjected to a conductive material anneal
08/16/2005US6930028 Antireflective structure and method
08/16/2005US6930027 Method of manufacturing a semiconductor component
08/16/2005US6930026 Method of forming a semiconductor wafer having a crystalline layer thereon containing silicon, germanium and carbon
08/16/2005US6930023 Semiconductor wafer thinning method, and thin semiconductor wafer
08/16/2005US6930020 Method for fabricating large area flexible electronics
08/16/2005US6930019 Method for forming MOS transistor
08/16/2005US6930018 Shallow trench isolation structure and method
08/16/2005US6930016 Position detection apparatus and method, exposure apparatus, and device manufacturing method
08/16/2005US6930015 Diffusion-enhanced crystallization of amorphous materials to improve surface roughness
08/16/2005US6930014 Method of forming semiconductor device capacitor bottom electrode having cylindrical shape
08/16/2005US6930013 Method of forming a capacitor of an integrated circuit device
08/16/2005US6930012 Semiconductor memory with trench capacitor and method of manufacturing the same
08/16/2005US6930011 Semiconductor device with a bipolar transistor, and method of manufacturing such a device
08/16/2005US6930010 Method of forming a conductive structure in a semiconductor material
08/16/2005US6930009 Laser synthesized wide-bandgap semiconductor electronic devices and circuits
08/16/2005US6930008 Method of fabricating a complementary bipolar junction transistor
08/16/2005US6930007 Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance
08/16/2005US6930006 Electronic circuit structure with improved dielectric properties
08/16/2005US6930005 Low cost fabrication method for high voltage, high drain current MOS transistor
08/16/2005US6930004 Self-aligned drain/channel junction in vertical pass transistor DRAM cell design for device scaling
08/16/2005US6930003 Method of manufacturing semiconductor device
08/16/2005US6930002 Method for programming single-poly EPROM at low operation voltages
08/16/2005US6930001 Method for manufacturing NAND flash device
08/16/2005US6930000 Method of manufacturing semiconductor device
08/16/2005US6929999 Method of manufacturing semiconductor device with contact body extending in direction of bit line to contact storage node
08/16/2005US6929998 Method for forming bottle-shaped trench
08/16/2005US6929997 Triple metal line 1T/1C ferroelectric memory device and method for fabrication thereof
08/16/2005US6929996 Corner rounding process for partial vertical transistor
08/16/2005US6929995 Method of forming high voltage metal oxide semiconductor transistor
08/16/2005US6929994 Method for manufacturing semiconductor device that includes well formation
08/16/2005US6929993 Methods of forming memory cells and arrays having underlying source-line connections
08/16/2005US6929992 Strained silicon MOSFETs having NMOS gates with work functions for compensating NMOS threshold voltage shift
08/16/2005US6929991 Reliable semiconductor device and method of manufacturing the same
08/16/2005US6929990 MOSFET with a thin gate insulating film
08/16/2005US6929989 Semiconductor device and manufacturing method thereof
08/16/2005US6929988 Method of making an ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge
08/16/2005US6929987 Microelectronic device fabrication method
08/16/2005US6929986 Semiconductor device, display device, and method of manufacturing the same
08/16/2005US6929984 Gettering using voids formed by surface transformation
08/16/2005US6929982 Patterning layers comprised of spin-on ceramic films
08/16/2005US6929980 Manufacturing method of flip chip package
08/16/2005US6929979 Method for packaging semiconductor device
08/16/2005US6929978 Method of fabricating an integrated circuit package utilizing a conductive structure for improving the bond strength between an IC package and a printed circuit board
08/16/2005US6929977 Method of introducing resin for electronic component and apparatus used therefor
08/16/2005US6929974 Feedthrough design and method for a hermetically sealed microdevice
08/16/2005US6929971 Semiconductor device and its manufacturing method
08/16/2005US6929970 Process for preparing nano-porous metal oxide semiconductor layers
08/16/2005US6929964 Method of monitoring introduction on interfacial species
08/16/2005US6929963 Semiconductor component and method of manufacture and monitoring
08/16/2005US6929962 System and method for wafer acceptance test configuration
08/16/2005US6929961 Dual function array feature for CMP process control and inspection
08/16/2005US6929958 Method to make small isolated features with pseudo-planarization for TMR and MRAM applications
08/16/2005US6929957 Magnetic random access memory designs with patterned and stabilized magnetic shields
08/16/2005US6929956 Ferroelectric random access memory device and fabrication method therefor
08/16/2005US6929903 Developing in a state in which the resist dissolution concentration in the developing solution is the estimated dissolution concentration or less; semiconductor manufacturing
08/16/2005US6929902 Anti-reflect layer (especially silicon nitride) is interposed between the substrate and the defective photoresist layer; removing the defective layer with oxygen plasma; alkaline solution treatment to react with the anti-reflect layer
08/16/2005US6929896 Iodonium or sulfonium compounds as photosensitive acid donors in the preparation of colour filters or chemically amplified resists
08/16/2005US6929892 Method of monitoring an exposure process
08/16/2005US6929874 Aluminum nitride sintered body, ceramic substrate, ceramic heater and electrostatic chuck
08/16/2005US6929867 Hafnium nitride buffer layers for growth of GaN on silicon
08/16/2005US6929856 Composed mainly of a polyimide, especially a polyimidesiloxane, and has a peel strength of 0.02 N/mm or greater at near room temperature (20-50 degrees C.) and a cured peel strength of 0.3 N/mm or greater.
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