Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
09/2005
09/01/2005US20050190353 Lithographic apparatus and device manufacturing method
09/01/2005US20050190352 Method and apparatus for forming pattern on thin substrate or the like
09/01/2005US20050190351 Lithographic apparatus and device manufacturing method
09/01/2005US20050190350 Exposure apparatus and method
09/01/2005US20050190348 Device and method for testing an exposure apparatus
09/01/2005US20050190339 Fixing device, method of fixing substrate and apparatus and method for manufacturing a liquid crystal display panel using the same
09/01/2005US20050190315 Liquid crystal display device
09/01/2005US20050190314 Dielectric reflector for amorphous silicon crystallization
09/01/2005US20050190311 Liquid crystal display device
09/01/2005US20050190310 Inspection method and apparatus using charged particle beam
09/01/2005US20050190130 Active matrix type display
09/01/2005US20050190023 Micro-switching element fabrication method and micro-switching element
09/01/2005US20050190020 Reducing line to line capacitance using oriented dielectric films
09/01/2005US20050189989 Power amplification apparatus, and mobile communication terminal apparatus
09/01/2005US20050189966 Output stage resistant against high voltage swings
09/01/2005US20050189959 Electrochemical fabrication process for forming multilayer multimaterial microprobe structures
09/01/2005US20050189955 Semiconductor device test probe having improved tip portion
09/01/2005US20050189883 TFT, flat panel display device having the same, method of manufacturing TFT, method of manufacturing flat panel display device, and method of manufacturing donor sheet
09/01/2005US20050189660 Source drain and extension dopant concentration
09/01/2005US20050189659 Semiconductor package free of substrate and fabrication method thereof
09/01/2005US20050189658 Semiconductor device assembly process
09/01/2005US20050189656 Micro-vias for electronic packaging
09/01/2005US20050189655 Integrated circuit chip utilizing carbon nanotube composite interconnection vias
09/01/2005US20050189654 Semiconductor device and method of fabricating the same
09/01/2005US20050189653 Dual damascene intermediate structure and method of fabricating same
09/01/2005US20050189652 Method for fabricating a silicide film, multilayered intermediate structure and multilayered structure
09/01/2005US20050189651 Contact formation method and semiconductor device
09/01/2005US20050189650 Low fabrication cost, high performance, high reliability chip scale package
09/01/2005US20050189649 LSI package, LSI element testing method, and semiconductor device manufacturing method
09/01/2005US20050189646 Packaged die on PCB with heat sink encapsulant and methods
09/01/2005US20050189642 Apparatus for encapsulating a multi-chip substrate array
09/01/2005US20050189641 Semiconductor package
09/01/2005US20050189637 Semiconductor device and manufacturing method thereof
09/01/2005US20050189636 Packaging substrates for integrated circuits and soldering methods
09/01/2005US20050189634 Semiconductor module and method of manufacturing thereof
09/01/2005US20050189633 Chip package structure
09/01/2005US20050189632 Sealed three dimensional metal bonded integrated circuits
09/01/2005US20050189629 Method of manufacturing a semiconductor device
09/01/2005US20050189627 Method of surface mounting a semiconductor device
09/01/2005US20050189620 Manufacturing method for semiconductor device, and system to which semiconductor is applied
09/01/2005US20050189617 Bipolar transistor having multiple interceptors
09/01/2005US20050189616 Techniques for reducing bowing in power transistor devices
09/01/2005US20050189615 Non-continuous encapsulation layer for mim capacitor
09/01/2005US20050189613 Semiconductor device as electrically programmable fuse element and method of programming the same
09/01/2005US20050189612 Method for forming copper fuse links
09/01/2005US20050189611 High frequency passive element
09/01/2005US20050189610 Semiconductor device and method of manufacturing the same
09/01/2005US20050189609 Embedded semiconductor product with dual depth isolation regions
09/01/2005US20050189608 [shallow trench isolation and method of forming the same]
09/01/2005US20050189607 Upper-layer metal power standard cell
09/01/2005US20050189606 Semiconductor device and method for fabricating the same
09/01/2005US20050189605 Integrated circuit logic with self compensating shapes
09/01/2005US20050189604 Integrated circuit logic with self compensating block delays
09/01/2005US20050189603 Semiconductor device
09/01/2005US20050189602 Semiconductor device
09/01/2005US20050189600 Semiconductor device having gate electrode of staked structure including polysilicon layer and metal layer and method of manufacturing the same
09/01/2005US20050189599 Semiconductor device having a silicided gate electrode and method of manufacture therefor
09/01/2005US20050189598 Logic embedded-memory integrated circuits
09/01/2005US20050189597 Semiconductor device featuring multi-layered electrode structure
09/01/2005US20050189596 Manufacturing method of the semiconductor device and the semiconductor device
09/01/2005US20050189595 Semiconductor device comprising transistor pair isolated by trench isolation
09/01/2005US20050189592 Semiconductor device and method of manufacturing the same
09/01/2005US20050189590 Semiconductor device and method of manufacturing the same
09/01/2005US20050189588 Semiconductor structure
09/01/2005US20050189587 LDMOS transistor
09/01/2005US20050189586 DMOS device with a programmable threshold voltage
09/01/2005US20050189585 Self aligned contact structure for trench device
09/01/2005US20050189584 Semiconductor device and manufacturing method of the same
09/01/2005US20050189583 Field effect transistors having multiple stacked channels
09/01/2005US20050189582 Charge trapping memory cell and fabrication method
09/01/2005US20050189581 Method of fabricating memory cell in semiconductor device
09/01/2005US20050189580 Method of forming a low voltage gate oxide layer and tunnel oxide layer in an EEPROM cell
09/01/2005US20050189579 Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device
09/01/2005US20050189578 Flat panel display with high capacitance and method of manufacturing the same
09/01/2005US20050189577 Metal-insulator-metal (MIM) capacitor structure formed with dual damascene structure
09/01/2005US20050189576 Semiconductor storage device
09/01/2005US20050189575 Semiconductor fabrication that includes surface tension control
09/01/2005US20050189572 Semiconductor device and method of manufacturing the same
09/01/2005US20050189571 Ferroelectric memory
09/01/2005US20050189570 Semiconductor device and method of producing the same
09/01/2005US20050189567 Wire loop, semiconductor device having same, wire bonding method and wire bonding apparatus
09/01/2005US20050189565 Bipolar transistor and method of manufacturing the same
09/01/2005US20050189563 Strained-semiconductor-on-insulator device structures
09/01/2005US20050189562 Integrated III-nitride power devices
09/01/2005US20050189560 Integrated circuit with enhancement mode pseudomorphic high electron mobility transistors having on-chip electrostatic discharge protection
09/01/2005US20050189559 Semiconductor device
09/01/2005US20050189547 Semiconductor light-emitting device with isolation trenches, and method of fabricating same
09/01/2005US20050189544 Methods of forming a high conductivity diamond film and structures formed thereby
09/01/2005US20050189543 Semiconductor device and method of fabricating the same
09/01/2005US20050189542 Crystalline film and its manufacture method using laser
09/01/2005US20050189536 Self-assembly organic dielectric layers based on phosphonic acid derivatives
09/01/2005US20050189534 Doped semiconductor nanocrystals
09/01/2005US20050189517 includes phosphors having a small particle size, narrow particle size distribution, spherical morphology and good crystallinity; utilized in cathode ray tube (CRT) screens for televisions and similar devices
09/01/2005US20050189502 Alignment systems and methods for lithographic systems
09/01/2005US20050189501 Charged particle system and a method for measuring image magnification
09/01/2005US20050189489 Method for matching two measurement methods for measuring structure widths on a substrate
09/01/2005US20050189482 3-grid neutral beam source used for etching semiconductor device
09/01/2005US20050189340 Silicon layer for uniformizing temperature during photo-annealing
09/01/2005US20050189332 Chip package sealing method
09/01/2005US20050189329 Laser thermal processing with laser diode radiation