Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2006
06/27/2006US7068093 Semiconductor integrated circuit with voltage adjusting circuit
06/27/2006US7068082 Gate driving circuit and semiconductor device
06/27/2006US7068072 Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit
06/27/2006US7068069 Control circuit and reconfigurable logic block
06/27/2006US7068058 Semiconductor integrated circuit device with test element group circuit
06/27/2006US7068057 Low-current pogo probe card
06/27/2006US7067942 Linear motor, moving stage system, exposure apparatus, and device manufacturing method
06/27/2006US7067931 Self-compensating mark design for stepper alignment
06/27/2006US7067930 containing core-shell polymers of alkyl (meth)acrylates; glass transition temperature of the core is up to -10 degrees C., of the shell is 80-150 degrees C., with a particle size of 0.1-1.0 mu m; adherent to surfaces of silicon chips, especially polyimide resins; useful as sealant for flip chips
06/27/2006US7067929 Semiconductor wafer, semiconductor device, circuit board, electronic instrument, and method for manufacturing semiconductor device
06/27/2006US7067928 Method of forming a bonding pad structure
06/27/2006US7067926 Semiconductor chip and method for manufacturing the same
06/27/2006US7067925 Barrier film integrity on porous low k dielectrics by application of a hydrocarbon plasma treatment
06/27/2006US7067924 Nickel bonding cap over copper metalized bondpads
06/27/2006US7067923 Semiconductor device having hall-effect and manufacturing method thereof
06/27/2006US7067922 Semiconductor device
06/27/2006US7067921 Method for fabricating a metal-insulator-metal capacitor in a semiconductor device
06/27/2006US7067920 Semiconductor device and method of fabricating the same
06/27/2006US7067919 Semiconductor device
06/27/2006US7067917 Gradient barrier layer for copper back-end-of-line technology
06/27/2006US7067916 Extension of fatigue life for C4 solder ball to chip connection
06/27/2006US7067915 Electronic device with external contact elements and method for producing a plurality of the devices
06/27/2006US7067909 Multi-layer integrated semiconductor structure having an electrical shielding portion
06/27/2006US7067905 Packaged microelectronic devices including first and second casings
06/27/2006US7067902 Building metal pillars in a chip for structure support
06/27/2006US7067900 Insulated gate bipolar transistor having a reduced tail current and method of fabricating the same
06/27/2006US7067899 Semiconductor integrated circuit device
06/27/2006US7067894 Semiconductor devices using anti-reflective coatings
06/27/2006US7067889 Method for manufacturing semiconductor integrated circuit device
06/27/2006US7067888 Semiconductor device and a method of manufacturing the same
06/27/2006US7067884 Electrostatic discharge device
06/27/2006US7067881 Semiconductor device
06/27/2006US7067880 Transistor gate structure
06/27/2006US7067878 Field effect transistor
06/27/2006US7067875 Semiconductor integrated circuit device and its manufacturing method
06/27/2006US7067874 Semiconductor device including trench with at least one of an edge of an opening and a bottom surface being round
06/27/2006US7067872 Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same
06/27/2006US7067871 Stacked gate semiconductor memory
06/27/2006US7067870 Power semiconductor switching element
06/27/2006US7067869 Adjustable 3D capacitor
06/27/2006US7067867 Large-area nonenabled macroelectronic substrates and uses therefor
06/27/2006US7067866 MRAM architecture and a method and system for fabricating MRAM memories utilizing the architecture
06/27/2006US7067864 SRAM having an improved capacitor
06/27/2006US7067861 Device and method for protecting against oxidation of a conductive layer in said device
06/27/2006US7067858 Heterojunction bipolar transistor with a base layer that contains bismuth
06/27/2006US7067857 Semiconductor device having led out conductor layers, manufacturing method of the same, and semiconductor module
06/27/2006US7067856 Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
06/27/2006US7067855 Semiconductor structure having an abrupt doping profile
06/27/2006US7067847 Semiconductor element
06/27/2006US7067845 Semiconductor device and method of manufacturing the same
06/27/2006US7067844 Electro-optical device
06/27/2006US7067843 Transparent oxide semiconductor thin film transistors
06/27/2006US7067837 Phase-change memory devices
06/27/2006US7067832 Extreme ultraviolet light source
06/27/2006US7067830 Multi-electron beam exposure method and apparatus
06/27/2006US7067826 Position detection method and apparatus
06/27/2006US7067813 Infrared absorption measurement method, infrared absorption measurement device, and method of manufacturing semiconductor device
06/27/2006US7067806 Scanning probe microscope and specimen observation method
06/27/2006US7067764 Mask for light exposure and method for manufacturing liquid crystal display apparatus employing same
06/27/2006US7067763 High speed, laser-based marking method and system for producing machine readable marks on workpieces and semiconductor devices with reduced subsurface damage produced thereby
06/27/2006US7067761 Semiconductor device manufacturing system for etching a semiconductor by plasma discharge
06/27/2006US7067465 Aqueous solutions of phosphoric acid and another acid; removal residues
06/27/2006US7067458 support substrate on which crystals cannot be epitaxially grown, e.g., fused quartz; anisotropic electrode layer e.g., Bi2Sr2CaCu2O8; and a dielectric layer formed by epitaxially growing a dielectric material containing a bismuth layer structured compound on the electrode layer, e.g., SrBi4Ti4O15
06/27/2006US7067442 Method to avoid threshold voltage shift in thicker dielectric films
06/27/2006US7067441 Damage-free resist removal process for ultra-low-k processing
06/27/2006US7067440 Gap fill for high aspect ratio structures
06/27/2006US7067439 ALD metal oxide deposition process using direct oxidation
06/27/2006US7067438 Atomic layer deposition method of forming an oxide comprising layer on a substrate
06/27/2006US7067437 Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same
06/27/2006US7067436 Method of forming silicon oxide film and forming apparatus thereof
06/27/2006US7067435 Method for etch-stop layer etching during damascene dielectric etching with low polymerization
06/27/2006US7067434 Hydrogen free integration of high-k gate dielectrics
06/27/2006US7067433 Method to reduce the fluorine contamination on the Al/Al-Cu pad by a post high cathod temperature plasma treatment
06/27/2006US7067432 Methodology for in-situ and real-time chamber condition monitoring and process recovery during plasma processing
06/27/2006US7067431 Method of forming damascene pattern in a semiconductor device
06/27/2006US7067430 Method of making relaxed silicon-germanium on insulator via layer transfer with stress reduction
06/27/2006US7067429 Processing method of forming MRAM circuitry
06/27/2006US7067428 Method for cleaning polysilicon
06/27/2006US7067427 Manufacturing method of semiconductor device
06/27/2006US7067426 Semiconductor processing methods
06/27/2006US7067425 Method of manufacturing flash memory device
06/27/2006US7067424 Method of manufacturing an electronic device
06/27/2006US7067423 Electroless plating apparatus, semiconductor wafer having bumps, semiconductor chip having bumps, methods of manufacturing the semiconductor wafer and the semiconductor chip, semiconductor device, circuit board, and electronic equipment
06/27/2006US7067422 Method of forming a tantalum-containing gate electrode structure
06/27/2006US7067421 Multilevel copper interconnect with double passivation
06/27/2006US7067420 Methods for forming a metal layer on a semiconductor
06/27/2006US7067419 Mask layer and dual damascene interconnect structure in a semiconductor device
06/27/2006US7067418 Interconnect structure and method for fabricating the same
06/27/2006US7067417 Methods of removing resistive remnants from contact holes using silicidation
06/27/2006US7067416 Method of forming a conductive contact
06/27/2006US7067415 Low k interlevel dielectric layer fabrication methods
06/27/2006US7067414 Low k interlevel dielectric layer fabrication methods
06/27/2006US7067413 Wire bonding method, semiconductor chip, and semiconductor package
06/27/2006US7067412 Semiconductor device and method of manufacturing the same
06/27/2006US7067411 Method to prevent metal oxide formation during polycide reoxidation
06/27/2006US7067410 Method of forming a metal silicide
06/27/2006US7067409 Plasma treatment at film layer to reduce sheet resistance and to improve via contact resistance
06/27/2006US7067408 Method for releasing stress during semiconductor device fabrication
06/27/2006US7067407 Method of growing electrical conductors
06/27/2006US7067406 Thermal conducting trench in a semiconductor structure and method for forming the same