Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2006
07/27/2006US20060162861 Method and control system for treating a hafnium-based dielectric processing system
07/27/2006US20060162850 Methods and apparatus for releasably attaching microfeature workpieces to support members
07/27/2006US20060162780 Pressure reduction process device, pressure reduction process method, and pressure regulation valve
07/27/2006US20060162766 Back-contacted solar cells with integral conductive vias and method of making
07/27/2006US20060162763 Photovoltaic apparatus and mass-producing apparatus for mass-producing spherical semiconductor particles
07/27/2006US20060162745 Substrate processing method and substrate processing device
07/27/2006US20060162661 Mixing energized and non-energized gases for silicon nitride deposition
07/27/2006US20060162660 Recovery processing method to be adopted in substrate processing apparatus, substrate processing apparatus and program
07/27/2006US20060162656 Reduced volume, high conductance process chamber
07/27/2006US20060162650 Coating apparatus and organic electronic device fabricating method
07/27/2006US20060162474 End face sensor and method of producing the same
07/27/2006US20060162270 Profiled rail and method for producing a profiled rail
07/27/2006US20060162261 Composition and associated method for catalyzing removal rates of dielectric films during chemical mechanical planarization
07/27/2006US20060162260 Cerium oxide abrasive and slurry containing the same
07/27/2006US20060162173 Scribing system with particle remover
07/27/2006US20060162172 Scribing tool and method
07/27/2006US20060162157 Economical high-frequency package
07/27/2006DE4341180B4 Verfahren zur Isolation einer Halbleiterschicht auf einem Isolator zur Festlegung eines aktiven Gebiets A method for isolating a semiconductor layer on an insulator establishing an active region
07/27/2006DE4308665B4 DRAM mit einer bidirektionalen globalen Bitleitung DRAM with a bidirectional global bit line
07/27/2006DE19916073B4 Dünnfilmtransistor und Verfahren zu seiner Herstellung A thin film transistor and method for its preparation
07/27/2006DE19720215B4 Verfahren zum Herstellen von Halbleiterbauteilen mit einem Graben-Gate mittels Seitenwandimplantation A method of producing semiconductor devices having a trench-gate side wall by means of implantation
07/27/2006DE19717358B4 Verfahren zur Bildung einer Isolationsschicht einer Halbleitereinrichtung A method of forming an insulating layer of a semiconductor device
07/27/2006DE19609107B4 Verfahren zum Herstellen von Siliziumwafern A method for producing silicon wafers
07/27/2006DE112004001162T5 Endeffektoren zum Handhaben von Halbleiterwafern End effectors for handling semiconductor wafers
07/27/2006DE10361135B4 Trenchtransistor und Verfahren zur Herstellung eines Trenchtransistors mit hochenergieimplantiertem Drain Trench transistor and method of manufacturing a trench transistor having drain hochenergieimplantiertem
07/27/2006DE10345768B4 Anschlussmittel und Verfahren zum Kontaktieren des Anschlussmittels Connection means and methods for contacting the connection means
07/27/2006DE10335153B4 Schaltungsanordnung auf einem Substrat, die einen Bestandteil eines Sensors aufweist, und Verfahren zum Herstellen der Schaltungsanordnung auf dem Substrat A circuit arrangement on a substrate having a part of a sensor and method for manufacturing the circuit arrangement on the substrate
07/27/2006DE10334547B4 Herstellungsverfahren für einen Grabenkondensator mit einem Isolationskragen, der über einen vergrabenen Kontakt einseitig mit einem Substrat elektrisch verbunden ist Manufacturing method for a grave capacitor with an insulation collar, which is electrically connected through a buried contact on one side with a substrate
07/27/2006DE10321496B4 Herstellungsverfahren für einen einseitig angeschlossenen Grabenkondensator Manufacturing method for a grave capacitor connected on one side
07/27/2006DE10319135B4 Verfahren zum Elektroplattieren von Kupfer über einer strukturierten dielektrischen Schicht, um die Prozess-Gleichförmigkeit eines nachfolgenden CMP-Prozesses zu verbessern A method for electroplating copper on a patterned dielectric layer in order to improve process uniformity of a subsequent CMP process
07/27/2006DE10310811B4 Herstellungsverfahren für einen Grabenkondensator mit einem Isolationskragen, der über einen vergrabenen Kontakt einseitig mit einem Substrat elektrisch verbunden ist Manufacturing method for a grave capacitor with an insulation collar, which is electrically connected through a buried contact on one side with a substrate
07/27/2006DE10308870B4 Bipolartransistor mit verbessertem Basis-Emitter-Übergang und Verfahren zur Herstellung Bipolar transistor with an improved base-emitter junction and methods for preparing
07/27/2006DE10214529B4 ROM-Speicheranordnung ROM memory device
07/27/2006DE10206148B4 Verfahren zur Ausbildung einer Diffusionssperrschicht in einem pMOS-Bauteil A method of forming a diffusion barrier layer in a PMOS device
07/27/2006DE102006002452A1 Halbleitervorrichtung und Verfahren zu ihrer Herstellung Semiconductor device and process for their preparation
07/27/2006DE102006001999A1 Signalneuverteilung unter Verwendung einer Brückenschicht für ein Mehrchipmodul Signalneuverteilung using a bridge layer for a multi-chip module
07/27/2006DE102006000766A1 CMP Kissen, das eine radial abwechselnde Rillensegmentkonfiguration aufweist CMP pad having a radially alternating grooves segment configuration
07/27/2006DE102006000615A1 Materialien mit hoher Dielektrizitätskonstante High dielectric constant materials
07/27/2006DE102005058692A1 Polierzusammensetzungen zur Verminderung der Erosion in Halbleiterwafern Polishing compositions for reducing erosion in semiconductor wafers
07/27/2006DE102005056702A1 TFT-Arraysubstrat und zugehöriges Herstellverfahren TFT array substrate manufacturing process and related
07/27/2006DE102005041648A1 Gate-controlled atomic switch has three electrodes immersed in electrolyte, and source and drain electrodes are connected by bridge consisting of one or more atoms that can be opened and closed
07/27/2006DE102005003248A1 Power transistor gate isolation testing method for semiconductor device, involves applying test potential to wire and another test potential between gate contact and source contact to determine faulty current
07/27/2006DE102005003184A1 Tri-tone mask for lithographic manufacturing of semiconductor device, has mask structure in chromium layer, halftone layer or glass layer, where structure is surrounded by strip of halftone layer with predetermined width
07/27/2006DE102005003183A1 Semiconductor structures manufacturing method, involves aligning main semiconductor structures perpendicular to dipole axis and manufacturing compound semiconductor structure by interconnecting two of main semiconductor structures
07/27/2006DE102005003125A1 High-frequency electrical circuit for multi-chip module, has electrical components mechanically connected with each other by sealing compound and provided with conductive strip layers, which electrically connects components with each other
07/27/2006DE102005002987A1 Leiterbahnstruktur zur Minimierung von thermomechanischen Belastungen Conductor track structure in order to minimize thermo-mechanical stress
07/27/2006DE102005002862A1 Fine ball grid array component manufacturing method, involves pressing grouting form for detection of lower housing part on solder ball side, and designing substrate surface as sealing area such that surface is provided with sealing units
07/27/2006DE102005002739A1 Verfahren zum Herstellen eines Feldeffekttransistors, Feldeffekttransistor und integrierte Schaltungsanordnung A method of manufacturing a field effect transistor, field effect transistor and integrated circuit arrangement
07/27/2006DE102005002707A1 Semiconductor component, has micro connecting unit to provide high frequency coupling of components and including three ply structure with two layers extending along common middle line and fixed on contact surface pairs of components
07/27/2006DE102005002550A1 Material structure e.g. wafer processing involves applying coating material on surface of wafer and to remaining photoresist, and removing photoresist such that material remains only in one region of surface of photoresist
07/27/2006DE102005002006A1 Device for producing three-dimensional structures of materials in the micro- or nano-meter region in micro-electronics production comprises a vacuum chamber containing a media chamber, a reaction chamber and a coupling unit
07/27/2006DE102005001718A1 Integrated circuit e.g. logical chip, arrangement, has wiring section with nano-structure between wiring-junction units and electrically insulating layer provided in section, where one unit and layer form channel between junction units
07/27/2006DE102004063532A1 Verfahren zur Herstellung von Gateisolationsschichten mit unterschiedlichen Eigenschaften A process for producing gate insulation layers with different properties
07/27/2006DE102004031744A1 Eine Technik zur Herstellung einer dielektrischen Zwischenschicht über einer Struktur mit eng beabstandeten Leitungen A technique for producing an interlayer dielectric layer over a structure with closely spaced lines
07/27/2006DE102004031436B4 Einrichtung und Verfahren zum Kalibrieren eines Halbleiter-Bauelement-Test-Systems, insbesondere einer probecard bzw. eines Halbleiter-Bauelement-Testgeräts Apparatus and method for calibrating a semiconductor device test system, in particular a probe card and a semiconductor device tester
07/27/2006DE102004028030B4 Katalytisches Beschichtungsverfahren für strukturierte Substratoberflächen und mit einer Siliziumdioxid-Dünnschicht beschichtetes Substrat mit einer strukturierten Oberfläche Catalytic coating method for structured substrate surface and coated with a silicon dioxide thin film substrate with a structured surface
07/27/2006DE102004008289B4 Roboterführungseinheit zur Bereitstellung einer Präzisionsbewegung eines Gegenstands Robot control unit for providing a precision movement of an object
07/27/2006DE102004007661B4 Verfahren, Vorrichtung und Computerprogrammprodukt zur Optimierung eines Layouts von Versorgungsleitungen A method, apparatus and computer program product for optimization of a layout of power supply lines
07/27/2006DE10144467B4 Elektronisches Sensorbauteil und Verfahren zu seiner Herstellung Electronic sensor component and method for its preparation
07/27/2006DE10131626B4 Verfahren zum Herstellen einer Halbleiterspeichereinrichtung A method of manufacturing a semiconductor memory device
07/27/2006DE10115228B4 Steuerung des anormalen Wachstums bei auf Dichlorsilan (DCS) basierenden CVD-Polycid WSix-Filmen Control the abnormal growth based on at dichlorosilane (DCS) CVD polycide WSi x films
07/27/2006DE10103779B4 Herstellung von Grabenisolierungs-Bereichen in einem Halbleitersubstrat Manufacture of grave Insulation regions in a semiconductor substrate
07/27/2006DE10041790B4 Verfahren und Vorrichtung zum Anordnen von Substraten und Prozessiereinrichtung für Substrate Method and apparatus for arranging substrates and processing device for substrates
07/27/2006DE10037452B4 Nachführschaltung Readjustment
07/27/2006CA2595713A1 Replication tools and related fabrication methods and apparatus
07/27/2006CA2572798A1 Systems and methods for harvesting and integrating nanowires
07/26/2006EP1684436A1 Synchronous parallel-to-serial converter
07/26/2006EP1684367A2 Display device
07/26/2006EP1684360A1 Thin film transistor and process for fabricating the same
07/26/2006EP1684359A2 Misfet
07/26/2006EP1684358A2 High voltage SOI semiconductor device
07/26/2006EP1684357A2 High voltage semiconductor devices
07/26/2006EP1684356A2 Bipolar junction transistor
07/26/2006EP1684343A2 Method for manufacturing a semiconductor memory device
07/26/2006EP1684342A2 Method for manufacturing a semiconductor memory device
07/26/2006EP1684341A2 Electric circuit and method of manufacturing an electric circuit
07/26/2006EP1684340A2 Method of bonding a semiconductor element on a metal substrate
07/26/2006EP1684339A2 Method of manufacturing semiconductor device and method of treating electrical connection section
07/26/2006EP1684338A1 Non-contact id card and manufacturing method thereof
07/26/2006EP1684337A1 Cleaning composition for semiconductor containing unsaturated dicarboxylic acid and ethylene urea and cleaning method
07/26/2006EP1684336A1 Heat treatment apparatus and heat treatment method
07/26/2006EP1684335A1 Process for producing silicon epitaxial wafer
07/26/2006EP1684334A2 Coating and developing system and coating and developing method
07/26/2006EP1684333A2 Coating and developing system and coating and developing method
07/26/2006EP1684109A1 Laser processing apparatus
07/26/2006EP1683994A2 Gas panel
07/26/2006EP1683897A1 Wafer with semiconductor layer and insolator layer below it, and method therefore
07/26/2006EP1683889A1 Surface treatment method and device
07/26/2006EP1683887A1 Film deposition apparatus having hole-like rotary filter plate for capturing fine particles, and film deposition method
07/26/2006EP1683822A1 Prepolymer, prepolymer composition, high molecular weight polymer having structure containing hole and electrically insulating film
07/26/2006EP1683821A1 Composite particles and production process thereof, aqueous dispersion composition for chemical polishing, and process for manufacture of semiconductor device
07/26/2006EP1683209A2 Encapsulation assembly for electronic devices
07/26/2006EP1683206A1 Light emitting devices with self aligned ohmic contact and methods of fabricating same
07/26/2006EP1683204A1 Radiation detector
07/26/2006EP1683202A1 Trench gate field effect devices
07/26/2006EP1683201A1 Methods of forming power semiconductor devices using boule-grown silicon carbide drift layers and power semiconductor devices formed thereby
07/26/2006EP1683199A2 Anti-stiction technique for thin film and wafer-bonded encapsulated microelectromechanical systems
07/26/2006EP1683198A2 Semiconductor device and manufacturing method thereof
07/26/2006EP1683195A1 Semiconductor surface protecting sheet and method
07/26/2006EP1683194A2 Line edge roughness reduction for trench etch