H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
11/2006
11/02/2006	WO2006114344A1 Semiconductor arrangement of mosfets
11/02/2006	WO2006114029A1 A mosfet having isolation structure for single chip integration and methods of manufacturing the same
11/02/2006	WO2006114005A1 A method for packaging integrated sensors
11/02/2006	WO2006113998A1 Production of light from sol-gel derived thin films made with lanthanide doped nanoparticles, and preparation thereof
11/02/2006	WO2006098109A9 Plasma doping method and device
11/02/2006	WO2006079964A3 Method of fabricating a dual-gate fet
11/02/2006	WO2006078382A3 Passivating metal etch structures
11/02/2006	WO2006076207A3 Light emitting diodes (leds) with improved light extraction by roughening
11/02/2006	WO2006065160A8 METHOD OF MANUFACTURING DOPED Inx AlyGa1-x-yN EPITAXIAL LAYERS, DOPED InxAlyGa1-x-yN EPITAXIAL LAYER AND SEMICONDUCTOR MULTI-LAYER STRUCTURE COMPRISING AT LEAST ONE DOPED InxALyGa1-x-yN EPITAXIAL LAYER, WHERE
11/02/2006	WO2006063958A3 Method for producing an electrode
11/02/2006	WO2006062930A3 Method and system for fast filling of templates for imprint lithography using on template dispense
11/02/2006	WO2006034686A3 Method for producing a thin-film semiconductor chip
11/02/2006	WO2006023300A3 Methods of assembly for a semiconductor light emitting device package
11/02/2006	WO2006023019A3 Method of making a double gate semiconductor device with self-aligned gates and structure thereof
11/02/2006	WO2006022859A3 A spintronic device having a carbon nanotube array-based spacer layer and method of forming same
11/02/2006	WO2005104253A8 Laser patterning of light emitting devices and patterned light emitting devices
11/02/2006	WO2004023528A3 A thinned semiconductor wafer and die and corresponding method
11/02/2006	US20060248619 Method of preparing silver nano-structure by means of scanning turnneling microscopy
11/02/2006	US20060248543 Method and graphic engine chip for drawing processing
11/02/2006	US20060247813 Vacuum clamping detection method and vacuum clamping detector
11/02/2006	US20060247354 Method of manufacturing nanoscale metal oxide particles
11/02/2006	US20060247346 has high etching resistance and attains high resolution
11/02/2006	US20060246741 ATOMIC LAYER DEPOSITED NANOLAMINATES OF HfO2/ZrO2 FILMS AS GATE DIELECTRICS
11/02/2006	US20060246740 Removal of charged defects from metal oxide-gate stacks
11/02/2006	US20060246739 Method for Fabricating Dielectric Layer Doped with Nitrogen
11/02/2006	US20060246738 Semiconductor device and method for manufacturing the same
11/02/2006	US20060246737 New low dielectric (low k) barrier films with oxygen doping by plasma-enhanced chemical vapor deposition (pecvd)
11/02/2006	US20060246736 Methods for making nearly planar dielectric films in integrated circuits
11/02/2006	US20060246735 Film-forming apparatus component and method for cleaning same
11/02/2006	US20060246734 Methods of forming patterned photoresist layers over semiconductor substrates
11/02/2006	US20060246733 Method for making integrated circuits
11/02/2006	US20060246732 Method of uniformly etching refractory metals, refractory metal alloys and refractory metal silicides
11/02/2006	US20060246731 Semiconductor device fabrication method
11/02/2006	US20060246730 Method for fabricating transistor of semiconductor device
11/02/2006	US20060246729 Method for treating a structure to obtain an internal space and structure having an internal space
11/02/2006	US20060246728 Etching method using an at least semi-solid media
11/02/2006	US20060246727 Integrated dual damascene clean apparatus and process
11/02/2006	US20060246726 Making contact with the emitter contact of a semiconductor
11/02/2006	US20060246725 Hardening of copper to improve copper CMP performance
11/02/2006	US20060246724 Method for polishing wafer
11/02/2006	US20060246723 Slurry composition for chemical mechanical polishing, method for planarization of surface of semiconductor element using the same, and method for controlling selection ratio of slurry composition
11/02/2006	US20060246722 Etching technique for the fabrication of thin (AI, In, Ga)N layers
11/02/2006	US20060246721 Technique for forming interconnect structures with reduced electro and stress migration and/or resistivity
11/02/2006	US20060246720 Method to improve thermal stability of silicides with additives
11/02/2006	US20060246719 Inter-metal dielectric fill
11/02/2006	US20060246718 Technique for forming self-aligned vias in a metallization layer
11/02/2006	US20060246717 Method for fabricating a dual damascene and polymer removal
11/02/2006	US20060246716 Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS dielectric formation
11/02/2006	US20060246715 Semiconductor device structure and method for reducing hot carrier effect of mos transistor
11/02/2006	US20060246714 Method of forming a conductive contact
11/02/2006	US20060246713 Wiring line structure and method for forming the same
11/02/2006	US20060246712 Dual resistance heater for phase change devices and manufacturing method thereof
11/02/2006	US20060246711 Method of patterning a low-k dielectric using a hard mask
11/02/2006	US20060246710 Methods of fabricating semiconductor devices including contact plugs having laterally extending portions and related devices
11/02/2006	US20060246709 Methods of forming semiconductor devices having stacked transistors and related devices
11/02/2006	US20060246708 Method for fabricating semiconductor device with metal line
11/02/2006	US20060246707 Integrated circuit and method of manufacture
11/02/2006	US20060246706 Conductive bump structure for semiconductor device and fabrication method thereof
11/02/2006	US20060246705 Methods of forming wire bonds for semiconductor constructions
11/02/2006	US20060246704 Multi-chip module and method of manufacture
11/02/2006	US20060246703 Post bump passivation for soft error protection
11/02/2006	US20060246702 Non-solder mask defined (nsmd) type wiring substrate for ball grid array (bga) package and method for manufacturing such a wiring substrate
11/02/2006	US20060246701 Method for manufacturing clad components
11/02/2006	US20060246700 Migration enhanced epitaxy fabrication of active regions having quantum wells
11/02/2006	US20060246699 Process for electroless copper deposition on a ruthenium seed
11/02/2006	US20060246698 Process to make high-K transistor dielectrics
11/02/2006	US20060246697 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects
11/02/2006	US20060246696 Method of forming a chalcogenide material containing device
11/02/2006	US20060246695 Flip chip method
11/02/2006	US20060246694 Laser thermal annealing of lightly doped silicon substrates
11/02/2006	US20060246693 Method for manufacturing semiconductor device and laser irradiation apparatus
11/02/2006	US20060246692 Semiconductor sensor and method for manufacturing same
11/02/2006	US20060246691 Signal and/or ground planes with double buried insulator layers and fabrication process
11/02/2006	US20060246690 Electro-chemical deposition system
11/02/2006	US20060246689 Soi wafer and process for producing the same
11/02/2006	US20060246688 Semiconductor film manufacturing method and substrate manufacturing method
11/02/2006	US20060246687 Method for producing a semiconductor component
11/02/2006	US20060246686 Multiple etch-stop layer deposition scheme and materials
11/02/2006	US20060246685 Semiconductor device fabrication method
11/02/2006	US20060246684 Method of manufacturing semiconductor device
11/02/2006	US20060246683 Integrated equipment set for forming a low K dielectric interconnect on a substrate
11/02/2006	US20060246682 Product and method for integration of deep trench mesh and structures under a bond pad
11/02/2006	US20060246681 Sacrificial benzocyclobutene/norbornene polymers for making air gap semiconductor devices
11/02/2006	US20060246680 Stable PD-SOI devices and methods
11/02/2006	US20060246679 Forming integrated circuits using selective deposition of undoped silicon film seeded in chlorine and hydride gas
11/02/2006	US20060246678 Methods of forming a plurality of capacitors
11/02/2006	US20060246677 Methods of forming spaced conductive regions, and methods of forming capacitor constructions
11/02/2006	US20060246676 Semiconductor device and method of manufacturing the same
11/02/2006	US20060246675 Methods of forming capacitor constructions comprising perovskite-type dielectric materials
11/02/2006	US20060246674 Passive element chip and manufacturing method thereof, and highly integrated module and manufacturing method thereof
11/02/2006	US20060246673 Semiconductor device comprising extensions produced from material with a low melting point
11/02/2006	US20060246672 Method of forming a locally strained transistor
11/02/2006	US20060246671 Method of fabricating a transistor having a triple channel in a memory device
11/02/2006	US20060246670 Schottky device and method of forming
11/02/2006	US20060246669 Method for fabricating semiconductor devices having dual gate oxide layer
11/02/2006	US20060246668 Method for Improving the Thermal Stability of Silicide
11/02/2006	US20060246667 Method for reducing single bit data loss in a memory circuit
11/02/2006	US20060246666 Method of fabricating flash memory with u-shape floating gate
11/02/2006	US20060246665 Manufacturing process of an interpoly dielectric structure for non-volatile semiconductor integrated memories
11/02/2006	US20060246664 Memory with metal-insulator-metal tunneling program and erase

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