Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2008
06/26/2008US20080153283 Soluble hard mask for interlayer dielectric patterning
06/26/2008US20080153282 Method for preparing a metal feature surface
06/26/2008US20080153281 Fabrication for electroplating thick metal pads
06/26/2008US20080153280 Reactive sputter deposition of a transparent conductive film
06/26/2008US20080153279 Method For Manufacturing Semiconductor Device
06/26/2008US20080153278 Doped Single Crystal Silicon Silicided eFuse
06/26/2008US20080153277 Recess gate pattern having a sufficient margin between an edge of an active region and a neighboring recess region, to prevent damage generated in the edge of the active region when the recess region is formed to improve the characteristics of a device
06/26/2008US20080153276 Method for Manufacturing Semiconductor Device
06/26/2008US20080153275 Non-uniform ion implantation apparatus and method thereof
06/26/2008US20080153274 Deep bitline implant to avoid program disturb
06/26/2008US20080153273 Method for manufacturing a semiconductor device having improved across chip implant uniformity
06/26/2008US20080153272 Method for manufacturing SOI substrate
06/26/2008US20080153271 Safe handling of low energy, high dose arsenic, phosphorus, and boron implanted wafers
06/26/2008US20080153270 Method for tuning epitaxial growth by interfacial doping and structure including same
06/26/2008US20080153269 Thin oxide dummy tiling as charge protection
06/26/2008US20080153268 Atmosheric Pressure Chemical Vapor Deposition
06/26/2008US20080153267 Method for manufacturing a soi substrate associating silicon based areas and gaas based areas
06/26/2008US20080153266 Method to improve the selective epitaxial growth (seg) process
06/26/2008US20080153265 Semiconductor Device Manufactured Using an Etch to Separate Wafer into Dies and Increase Device Space on a Wafer
06/26/2008US20080153264 Wafer dividing method
06/26/2008US20080153263 Singulation method of semiconductor device
06/26/2008US20080153262 Wafer system with partial cuts
06/26/2008US20080153261 Method and device for producing semiconductor wafers of silicon
06/26/2008US20080153260 Semiconductor Wafer Sawing System and Method
06/26/2008US20080153259 Soi wafer and method for producing it
06/26/2008US20080153258 Process and device for bonding wafers
06/26/2008US20080153257 Method for producing a semiconductor-on-insulator structure
06/26/2008US20080153256 Methods and systems for nitridation of STI liner oxide in semiconductor devices
06/26/2008US20080153255 Method of Forming Device Isolation Film of Semiconductor Device
06/26/2008US20080153254 Semiconductor device and method for manufacturing semiconductor device
06/26/2008US20080153253 Chemical mechanical polishing process and method of fabricating semiconductor device using the same
06/26/2008US20080153252 Method And Apparatus For Providing Void Structures
06/26/2008US20080153251 Method of fabricating a mixed substrate
06/26/2008US20080153250 Method and structures for indexing dice
06/26/2008US20080153249 Method for fabricating semiconductor wafer with enhanced alignment performance
06/26/2008US20080153248 Method for manufacturing semiconductor device
06/26/2008US20080153247 Method For Manufacturing Semiconductor Device
06/26/2008US20080153246 Tridimensional integrated resistor
06/26/2008US20080153245 Semiconductor Device and Method of Forming Passive Devices
06/26/2008US20080153244 Method for manufacturing passive components
06/26/2008US20080153243 Blanket implant diode
06/26/2008US20080153242 Printed metal mask for UV, e-beam, ion-beam and X-ray patterning
06/26/2008US20080153241 Method for forming fully silicided gates
06/26/2008US20080153240 Method for Fabricating Semiconductor Device
06/26/2008US20080153239 Mask set for making a butting contact between two field effect transistors (FET); involves use of a heavily doped region of a second conductivity type that overrides the lightly doped region of a first conductivity type, and divides the heavily doped region of the first conductivity type into two areas
06/26/2008US20080153238 Method for forming a most device with reduced transient enhanced diffusion
06/26/2008US20080153237 Selective etch for patterning a semiconductor film deposited non-selectively
06/26/2008US20080153236 Flash memory devices and methods for fabricating the same
06/26/2008US20080153235 Insulated gate type semiconductor device and method for fabricating the same
06/26/2008US20080153234 Flash memory device and method of manufacturing the same
06/26/2008US20080153233 Flash memory with recessed floating gate
06/26/2008US20080153232 Manufacturing method of non-volatile memory
06/26/2008US20080153231 Manufacturing method of non-volatile memory
06/26/2008US20080153230 Method for fabricating flash memory device
06/26/2008US20080153229 Method for fabricating flash memory device
06/26/2008US20080153228 Methods for fabricating a memory device including a dual bit memory cell
06/26/2008US20080153227 Nand flash memory device and method of manufacturing the same
06/26/2008US20080153226 Method of Forming a Flash NAND Memory Cell Array With Charge Storage Elements Positioned in Trenches
06/26/2008US20080153225 Non-Volatile Memory In CMOS Logic Process
06/26/2008US20080153224 Integrated circuit system with memory system
06/26/2008US20080153223 Using thick spacer for bitline implant then remove
06/26/2008US20080153222 Methods for fabricating a split charge storage node semiconductor memory
06/26/2008US20080153221 Use of a Single Mask During the Formation of a Transistor's Drain Extension and Recessed Strained Epi Regions
06/26/2008US20080153220 Method for fabricating semiconductor devices using strained silicon bearing material
06/26/2008US20080153219 Method for Manufacturing CMOS Image Sensor
06/26/2008US20080153218 Recessed active for increased weffective transistors
06/26/2008US20080153217 Dual layer stress liner for mosfets
06/26/2008US20080153216 Method for manufacturing silicon carbide semiconductor device
06/26/2008US20080153215 LEAKAGE BARRIER FOR GaN BASED HEMT ACTIVE DEVICE
06/26/2008US20080153214 Method of manufacturing driving-device for unit pixel of organic light emitting display
06/26/2008US20080153213 Integrated circuit device, and method of fabricating same
06/26/2008US20080153212 Semiconductor device and manufacturing method thereof
06/26/2008US20080153211 Insulated power semiconductor module with reduced partial discharge and manufacturing method
06/26/2008US20080153210 Electronic assembly having an indium wetting layer on a thermally conductive body
06/26/2008US20080153209 Thinned die integrated circuit package
06/26/2008US20080153208 Semiconductor Package Block Mold and Method
06/26/2008US20080153207 Breakable interconnects and structures formed thereby
06/26/2008US20080153206 Chip mounting with flowable layer
06/26/2008US20080153205 Semiconductor device and a method for manufacturing the same
06/26/2008US20080153204 Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods
06/26/2008US20080153203 Semiconductor device manufacturing method
06/26/2008US20080153202 Flip chip mounting method by no-flow underfill
06/26/2008US20080153201 Flip chip mounting method by no-flow underfill having level control function
06/26/2008US20080153200 Stacked semiconductor components
06/26/2008US20080153199 Method of Field-Controlled Diffusion and Devices Formed Thereby
06/26/2008US20080153198 Method for Fabricating CMOS Image Sensor
06/26/2008US20080153197 Gate oxide film structure for a solid state image pick-up device
06/26/2008US20080153196 Image sensor device and method of manufacturing the same
06/26/2008US20080153191 III-Nitride Light Emitting Devices Grown on Templates to Reduce Strain
06/26/2008US20080153188 Apparatus and method for forming semiconductor layer
06/26/2008US20080153187 Chip-probing and bumping solutions for stacked dies having through-silicon vias
06/26/2008US20080153186 Evaluation Method for Crystal Defect in Silicon Single Crystal Wafer
06/26/2008US20080153185 Copper process methodology
06/26/2008US20080153184 Method for manufacturing integrated circuits by guardbanding die regions
06/26/2008US20080153183 Floating gate process methodology
06/26/2008US20080153182 Method and system to measure and compensate for substrate warpage during thermal processing
06/26/2008US20080153181 Substrate processing method, substrate processing system, and computer-readable recording medium recording program thereon
06/26/2008US20080153180 Integrated circuit wafer system with control strategy
06/26/2008US20080153179 Magnetic random access memory device and method of forming the same
06/26/2008US20080153178 Method for Fabricating MRAM