Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2008
07/08/2008US7397539 Transfer apparatus for transferring an object, lithographic apparatus employing such a transfer apparatus, and method of use thereof
07/08/2008US7397531 Lithographic apparatus and device manufacturing method
07/08/2008US7397139 Containing a curing agent and an inorganic filler, especially silica having a maximum diameter size of at least 32 mu m, an average particle size of 12 mu m or less and a specific surface area of 3.0 m2/g or more
07/08/2008US7397138 Semiconductor device
07/08/2008US7397135 Top layers of metal for high performance IC's
07/08/2008US7397134 Semiconductor device mounted on and electrically connected to circuit board
07/08/2008US7397131 Self-aligned semiconductor contact structures
07/08/2008US7397125 Semiconductor device with bonding pad support structure
07/08/2008US7397124 Process of metal interconnects
07/08/2008US7397123 Semiconductor integrated circuit device and process for manufacturing the same
07/08/2008US7397122 Metal wiring for semiconductor device and method for forming the same
07/08/2008US7397119 Wafer-level diamond spreader
07/08/2008US7397117 Chip package with die and substrate
07/08/2008US7397114 Semiconductor integrated circuit device and method of manufacturing the same
07/08/2008US7397113 Semiconductor device
07/08/2008US7397111 Semiconductor wafer, an electronic component, and a component carrier for producing the electronic component
07/08/2008US7397110 High resistance silicon wafer and its manufacturing method
07/08/2008US7397108 Bipolar transistor
07/08/2008US7397105 Apparatus to passivate inductively or capacitively coupled surface currents under capacitor structures
07/08/2008US7397104 Semiconductor integrated circuit device and a method of manufacturing the same
07/08/2008US7397099 Method of forming nano-sized MTJ cell without contact hole
07/08/2008US7397094 Semiconductor device and manufacturing method thereof
07/08/2008US7397090 Gate electrode architecture for improved work function tuning and method of manufacture
07/08/2008US7397087 FEOL/MEOL metal resistor for high end CMOS
07/08/2008US7397083 Trench fet with self aligned source and contact
07/08/2008US7397082 Semiconductor device having shallow trenches and method for manufacturing the same
07/08/2008US7397079 Non-volatile memory device and methods of forming the same
07/08/2008US7397078 Non-volatile semiconductor memory
07/08/2008US7397077 Magnetic memory devices having patterned heater layers therein that utilize thermally conductive sidewall materials to increase heat transfer when writing memory data
07/08/2008US7397075 Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors
07/08/2008US7397071 Tunnel transistor having spin-dependent transfer characteristics and non-volatile memory using the same
07/08/2008US7397070 Self-aligned transistor
07/08/2008US7397067 Microdisplay packaging system
07/08/2008US7397064 Semiconductor display device
07/08/2008US7397063 Semiconductor device
07/08/2008US7397040 Lithographic apparatus, device manufacturing method, and device manufactured thereby
07/08/2008US7397001 Multi-strand substrate for ball-grid array assemblies and method
07/08/2008US7397000 Wiring board and semiconductor package using the same
07/08/2008US7396806 For cleaning a semiconductor substrate after chemical mechanical polishing step
07/08/2008US7396781 Method and apparatus for adjusting feature size and position
07/08/2008US7396780 Method for laser processing of wafer
07/08/2008US7396779 Electronic apparatus, silicon-on-insulator integrated circuits, and fabrication methods
07/08/2008US7396778 Reacting a Lewis carboxylic acid and a Lewis amine base in solution to form a salt and polymerizing the salt; one of the reactants contains an adamantane ring and the other a carbocyclic aromatic ring; forming polybenzimidazoles and polybenzoxazoles; low dielectric constant and high mechanical strength
07/08/2008US7396777 Method of fabricating high-k dielectric layer having reduced impurity
07/08/2008US7396776 Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)
07/08/2008US7396775 Method for manufacturing semiconductor device
07/08/2008US7396774 Surface oxidizing a metal layer to form a metal oxide in a first oxidation state; reducing the metal oxide to form a surface of metal oxide in a first oxidation state and metal atom; and re-oxidizing to form a surface enriched with metal oxide in its higher oxidation state; especially forming CuO.
07/08/2008US7396773 Method for cleaning a gate stack
07/08/2008US7396772 Method for fabricating semiconductor device having capacitor
07/08/2008US7396771 Plasma etching apparatus and plasma etching method
07/08/2008US7396770 Post-parting etch to smooth silicon sliders
07/08/2008US7396769 Method for stripping photoresist from etched wafer
07/08/2008US7396768 Copper damascene chemical mechanical polishing (CMP) for thin film head writer fabrication
07/08/2008US7396767 Semiconductor structure including silicide regions and method of making same
07/08/2008US7396766 Low-temperature chemical vapor deposition of low-resistivity ruthenium layers
07/08/2008US7396765 Method of fabricating a liquid crystal display device
07/08/2008US7396764 Manufacturing method for forming all regions of the gate electrode silicided
07/08/2008US7396763 Semiconductor package using flexible film and method of manufacturing the same
07/08/2008US7396762 Interconnect structures with linear repair layers and methods for forming such interconnection structures
07/08/2008US7396761 Semiconductor device and method of manufacturing the same
07/08/2008US7396760 Method and system for reducing inter-layer capacitance in integrated circuits
07/08/2008US7396759 Protection of Cu damascene interconnects by formation of a self-aligned buffer layer
07/08/2008US7396758 Polycarbosilane buried etch stops in interconnect structures
07/08/2008US7396757 Interconnect structure with dielectric air gaps
07/08/2008US7396756 Top layers of metal for high performance IC's
07/08/2008US7396755 Process and integration scheme for a high sidewall coverage ultra-thin metal seed layer
07/08/2008US7396753 Semiconductor package substrate having bonding pads with plated layer thereon and process of manufacturing the same
07/08/2008US7396752 Method and apparatus for reducing cold joint defects in flip chip products
07/08/2008US7396751 Method for manufacturing semiconductor device
07/08/2008US7396750 Method and structure for contacting two adjacent GMR memory bit
07/08/2008US7396749 Method for contacting parts of a component integrated into a semiconductor substrate
07/08/2008US7396748 Semiconductor device includes gate insulating film having a high dielectric constant
07/08/2008US7396747 Hetero-integrated strained silicon n- and p-MOSFETs
07/08/2008US7396746 Methods for stable and repeatable ion implantation
07/08/2008US7396745 Formation of ultra-shallow junctions by gas-cluster ion irradiation
07/08/2008US7396744 Method of forming a semiconductor thin film
07/08/2008US7396743 Low temperature epitaxial growth of silicon-containing films using UV radiation
07/08/2008US7396742 Laser processing method for cutting a wafer-like object by using a laser to form modified regions within the object
07/08/2008US7396741 Method for connecting substrate and composite element
07/08/2008US7396740 Method of producing a device with a movable portion
07/08/2008US7396739 Method for integrating an electronic component or similar into a substrate
07/08/2008US7396738 Method of forming isolation structure of flash memory device
07/08/2008US7396737 Method of forming shallow trench isolation
07/08/2008US7396735 Semiconductor element heat dissipating member, semiconductor device using same, and method for manufacturing same
07/08/2008US7396734 Substrate manufacturing method
07/08/2008US7396733 Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device
07/08/2008US7396732 Formation of deep trench airgaps and related applications
07/08/2008US7396731 Method for preparing a non-self-aligned heterojunction bipolar transistor with a small emitter-to-base spacing
07/08/2008US7396730 Integrated circuit devices including an L-shaped depletion barrier layer adjacent opposite sides of a gate pattern and methods of forming the same
07/08/2008US7396729 Methods of forming semiconductor devices having a trench with beveled corners
07/08/2008US7396728 Methods of improving drive currents by employing strain inducing STI liners
07/08/2008US7396727 Transistor of semiconductor device and method for fabricating the same
07/08/2008US7396726 Methods of fabricating surrounded-channel transistors with directionally etched gate or insulator formation regions
07/08/2008US7396725 Method of manufacturing semiconductor device
07/08/2008US7396724 Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals
07/08/2008US7396723 Method of manufacturing EEPROM device
07/08/2008US7396722 Memory device with reduced cell area
07/08/2008US7396721 Method of fabricating a semiconductor device
07/08/2008US7396720 High coupling memory cell
07/08/2008US7396719 Method of forming high dielectric film using atomic layer deposition and method of manufacturing capacitor having the high dielectric film