Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
05/2009
05/22/2009WO2009063584A1 Programmable device, control method of device and information processing system
05/22/2009WO2009063583A1 Method for manufacturing flexible semiconductor device and flexible semiconductor device
05/22/2009WO2009063582A1 Semiconductor device and method for manufacturing the same
05/22/2009WO2009063562A1 Substrate transport device
05/22/2009WO2009063372A1 Thermal stress reduction
05/22/2009WO2009063288A1 Semiconductor structure having a protective layer
05/22/2009WO2009063046A1 Method for fabricating isolated integrated semiconductor structures
05/22/2009WO2009062887A1 Method and apparatus for ultrasonic bonding
05/22/2009WO2009062882A2 Method for manufacturing a solar cell with a surface-passivating dielectric double layer, and corresponding solar cell
05/22/2009WO2009062876A1 Reverse-conducting insulated gate bipolar transistor and corresponding manufacturing method
05/22/2009WO2009062757A1 Method for connecting two joining surfaces
05/22/2009WO2009062744A1 Method for dividing monocrystals
05/22/2009WO2009062397A1 Corrosion inhibitor for semiconductor chip metal substrate and use method thereof
05/22/2009WO2009046311A3 Composite slurries of nano silicon carbide and alumina
05/22/2009WO2009046219A3 Mosfet active area and edge termination area charge balance
05/22/2009WO2009046114A3 Two-transistor floating-body dynamic memory cell
05/22/2009WO2009045864A3 Methods of low-k dielectric and metal process integration
05/22/2009WO2009045635A3 Phase change memory structures
05/22/2009WO2009045371A3 Flip chip interconnection with double post
05/22/2009WO2009045050A3 Fluidic channel system and method for fabricating fine structure
05/22/2009WO2009043008A3 Methods and arrangement for creating models for fine-tuning recipes
05/22/2009WO2009042741A3 Method of enabling selective area plating on a substrate
05/22/2009WO2009042461A3 Techniques for optical ion beam metrology
05/22/2009WO2009036273A3 Horizontally depleted metal semiconductor field effect transistor
05/22/2009WO2009035868A3 Intelligent inspection based on test chip probe failure maps
05/22/2009WO2009035259A3 Apparatus for cutting processing memory card
05/22/2009WO2009034496A3 Wafer, method of manufacturing integrated circuits on a wafer, and method of storing data about said circuits
05/22/2009WO2009033126A3 Transport system with buffering
05/22/2009WO2009032575A3 Semiconductor device having reduced single bit fails and a method of manufacture thereof
05/22/2009WO2009023305A3 Method and system for printing aligned nanowires and other electrical devices
05/22/2009WO2009020572A3 Stack packages using reconstituted wafers
05/22/2009WO2009019266A3 Method of low-temperature transfer from a layer of self-assembled molecules
05/22/2009WO2009019265A3 Method of transferring a layer onto a liquid material
05/22/2009WO2009015984A3 Wafer joining method, wafer assemblage, and chip
05/22/2009WO2009013409A3 Method for producing a set of chips mechanically interconnected by means of a flexible connection
05/22/2009WO2008146869A3 Pattern forming method, pattern or mold formed thereby
05/22/2009WO2008134225A3 Integrated circuit switching device, structure and method of manufacture
05/22/2009WO2008051415A9 Method of manufacturing stacked chip packages
05/22/2009WO2007041454A3 Systems and methods for determination of endpoint of chamber cleaning processes
05/22/2009WO2007011438A3 Method and structure for reduction of soft error rates in integrated circuits
05/22/2009WO2007005189A3 Source side injection storage device and method therefor
05/22/2009WO2006130430A3 Photocathode structure and operation
05/22/2009WO2006127914A3 Trench-gate field effect transistors and methods of forming the same
05/21/2009US20090132880 Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test
05/21/2009US20090132078 Controlling device for substrate processing apparatus and method therefor
05/21/2009US20090131245 Controlled and selective formation of catalyst nanaoparticles
05/21/2009US20090130956 Polishing apparatus and polishing method
05/21/2009US20090130865 Method of patterning a layer using a pellicle
05/21/2009US20090130864 Systems and methods for flash annealing of semiconductor devices
05/21/2009US20090130863 Method and system for forming an air gap structure
05/21/2009US20090130862 Multi-functional cyclic silicate compound, siloxane-based polymer prepared from the compound and process of producing insulating film using the polymer
05/21/2009US20090130861 Dual damascene integration structures and method of forming improved dual damascene integration structures
05/21/2009US20090130860 Method of manufacturing a semiconductor device and processing apparatus
05/21/2009US20090130859 Semiconductor Device Manufacturing Method and Substrate Processing Apparatus
05/21/2009US20090130858 Deposition system and method using a delivery head separated from a substrate by gas pressure
05/21/2009US20090130857 Method of manufacturing a structure based on anisotropic etching, and silicon substrate with etching mask
05/21/2009US20090130856 Method for monitoring process drift using plasma characteristics
05/21/2009US20090130855 Phase change alloy etch
05/21/2009US20090130854 Patterning structure and method for semiconductor devices
05/21/2009US20090130853 Method for fabricating a deep trench in a substrate
05/21/2009US20090130852 Process for improving critical dimension uniformity of integrated circuit arrays
05/21/2009US20090130851 Method for manufacturing semiconductor device
05/21/2009US20090130850 Semiconductor Devices and Method of Fabricating the Same
05/21/2009US20090130849 Chemical mechanical polishing and wafer cleaning composition comprising amidoxime compounds and associated method for use
05/21/2009US20090130848 Semiconductor device and method for production thereof
05/21/2009US20090130847 Method of fabricating metal pattern without damaging insulation layer
05/21/2009US20090130846 Semiconductor device fabrication method
05/21/2009US20090130845 Direct electrodeposition of copper onto ta-alloy barriers
05/21/2009US20090130844 Method of Forming Metal Line of Semiconductor Device
05/21/2009US20090130843 Method of forming low-resistivity recessed features in copper metallization
05/21/2009US20090130842 Method of forming contact hole and method of manufacturing semiconductor memory device using the same
05/21/2009US20090130841 Method for forming contact in semiconductor device
05/21/2009US20090130840 Protected Solder Ball Joints in Wafer Level Chip-Scale Packaging
05/21/2009US20090130839 Manufacturing method of redistribution circuit structure
05/21/2009US20090130838 Method of forming conductive bumps
05/21/2009US20090130837 In situ deposition of a low k dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application
05/21/2009US20090130836 Method of fabricating flash cell
05/21/2009US20090130835 Method of manufacturing inverted t-shaped floating gate memory
05/21/2009US20090130834 Methods of forming impurity containing insulating films and flash memory devices including the same
05/21/2009US20090130833 Insulating buffer film and high dielectric constant semiconductor device and method for fabricating the same
05/21/2009US20090130832 Silicon surface structuring method
05/21/2009US20090130831 Semiconductor device and method of fabricating the same
05/21/2009US20090130830 Method for fabricating optical semiconductor device
05/21/2009US20090130829 Manufacturing method of semiconductor device and substrate processing apparatus
05/21/2009US20090130828 Method for Forming Voltage Sustaining Layer with Opposite-Doped Islands for Semiconductor Power Devices
05/21/2009US20090130827 Intrinsic amorphous silicon layer
05/21/2009US20090130826 Method of Forming a Semiconductor Device Having a Strained Silicon Layer on a Silicon-Germanium Layer
05/21/2009US20090130825 Joined Assembly, Wafer Holding Assembly, Attaching Structure Thereof and Method for Processing Wafer
05/21/2009US20090130824 Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
05/21/2009US20090130823 Method of forming semiconductor device including trench gate structure
05/21/2009US20090130822 Process for collective manufacturing of small volume high precision membranes and cavities
05/21/2009US20090130821 Three dimensional packaging with wafer-level bonding and chip-level repair
05/21/2009US20090130820 Method for manufacturing a semiconductor device
05/21/2009US20090130819 Method for manufacturing semiconductor device
05/21/2009US20090130818 Method for forming shallow trench isolation structure and method for preparing recessed gate structure using the same
05/21/2009US20090130817 Method to eliminate re-crystallization border defects generated during solid phase epitaxy of a dsb substrate
05/21/2009US20090130816 Method for manufacturing simox wafer and simox wafer manufactured thereby
05/21/2009US20090130815 Semiconductor device and method for fabricating the same
05/21/2009US20090130814 Semiconductor methods
05/21/2009US20090130813 Method and System to Provide a Polysilicon Capacitor with Improved Oxide Integrity