Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
02/2011
02/24/2011WO2011021244A1 Semiconductor device manufacturing method
02/24/2011WO2011020959A1 Method for manufacturing a light-emitting diode device for emitting light
02/24/2011WO2011020860A1 Method and device for determining a deformation of a disk-shaped workpiece, particularly a mold wafer
02/24/2011WO2011020712A2 Oligothiophenes derivatives
02/24/2011WO2011020632A1 Method for etching of silicon surfaces
02/24/2011WO2011020589A1 Method of inspecting and processing semiconductor wafers
02/24/2011WO2011020244A1 Packing method for bi-interface smart card
02/24/2011WO2011002811A3 Arrangement for identifying uncontrolled events at the process module level and methods thereof
02/24/2011WO2011002156A3 Apparatus for injecting melted solder into template cavities
02/24/2011WO2010151400A3 Fet with replacement gate structure and method of fabricating the same
02/24/2011WO2010148343A3 Methods and apparatus for simultaneously inspecting multiple array regions having different pitches
02/24/2011WO2010148271A3 Methods of making vertical junction field effect transistors and bipolar junction transistors without ion implantation and devices made therewith
02/24/2011WO2010147856A3 Sealed plasma coatings
02/24/2011WO2010144555A3 Adjusting current ratios in inductively coupled plasma processing systems
02/24/2011WO2010144303A3 Continuous feed chemical vapor deposition system
02/24/2011WO2010144290A3 Remote plasma processing of interface surfaces
02/24/2011WO2010138465A3 Pulse sequence for plating on thin seed layers
02/24/2011WO2010137899A3 Leadframe and method for manufacturing the same
02/24/2011WO2010136552A4 Device for transporting wafers and/or solar cells
02/24/2011WO2010135702A3 Low temperature gst process
02/24/2011WO2010135572A3 Method and apparatus for providing through silicon via (tsv) redundancy
02/24/2011WO2010135205A3 Integrated systems for interfacing with substrate container storage systems
02/24/2011WO2010135202A3 Substrate container storage system
02/24/2011WO2010134774A3 Half tone mask and manufacturing method of the same
02/24/2011WO2010132587A3 High voltage iii-nitride semiconductor devices
02/24/2011WO2010132338A3 Flip-chip underfill
02/24/2011WO2010129360A3 Semiconductor surface modification
02/24/2011WO2010129289A3 Decontamination of mocvd chamber using nh3 purge after in-situ cleaning
02/24/2011WO2010127298A3 Low oxygen content semiconductor material for surface enhanced photonic devices associated methods
02/24/2011WO2010127156A3 Method of forming in-situ pre-gan deposition layer in hvpe
02/24/2011WO2010127038A3 End effector for handling substrates
02/24/2011WO2010124217A3 Treatment of polishing pad window
02/24/2011WO2010106432A3 Deposition apparatus with high temperature rotatable target and method of operating thereof
02/24/2011WO2010092051A3 Integral process, from wafer production to module manufacturing, for producing wafers, solar cells, and solar modules
02/24/2011WO2008103611A3 Decoupled, multiple stage positioning system
02/24/2011WO2007117742A3 Batch processing system and method for performing chemical oxide removal
02/24/2011US20110047518 Pattern determining method
02/24/2011US20110046797 Semiconductor manufacturing system, controller, semiconductor manufacturing system control method, and processing liquid collection method
02/24/2011US20110045676 Remote plasma source seasoning
02/24/2011US20110045675 Substrate processing apparatus and producing method of semiconductor device
02/24/2011US20110045674 Method and apparatus for inline deposition of materials on a non-planar surface
02/24/2011US20110045673 Method for manufacturing a silicon surface with pyramidal texture
02/24/2011US20110045672 Multi-film stack etching with polymer passivation of an overlying etched layer
02/24/2011US20110045671 Composition for polishing surfaces of silicon dioxide
02/24/2011US20110045670 Method for manufacturing semiconductor device for preventing occurrence of short circuit between bit line contact plug and storage node contact plug
02/24/2011US20110045669 Method of manufacturing semiconductor device
02/24/2011US20110045668 Method of manufacturing wafer level device package
02/24/2011US20110045667 Gate of a transistor and method of forming the same
02/24/2011US20110045666 Method for fabricating semiconductor device
02/24/2011US20110045665 Reducing the creation of charge traps at gate dielectrics in mos transistors by performing a hydrogen treatment
02/24/2011US20110045664 Transistor structure having a trench drain
02/24/2011US20110045663 Field-effect transistor and method for fabricating the same
02/24/2011US20110045662 Low-temperature formation of layers of polycrystalline semiconductor material
02/24/2011US20110045661 Method for manufacturing nano-crystalline silicon material for semiconductor integrated circuits
02/24/2011US20110045660 Large-Area Nanoenabled Macroelectronic Substrates and Uses Therefor
02/24/2011US20110045659 Semiconductor buffer architecture for iii-v devices on silicon substrates
02/24/2011US20110045658 Method for fabricating a semi-polar nitride semiconductor
02/24/2011US20110045657 Method for fabricating rewritable three-dimensional memory device
02/24/2011US20110045656 System and process for dicing integrated circuits
02/24/2011US20110045655 Manufacturing method of semiconductor device and manufacturing apparatus of the same
02/24/2011US20110045654 Germanium layer polishing
02/24/2011US20110045653 Bonding method and bonding apparatus
02/24/2011US20110045652 Techniques to reduce substrate cross talk on mixed signal and rf circuit design
02/24/2011US20110045651 Semiconductor device and method of fabrication thereof
02/24/2011US20110045650 Method of manufacturing semiconductor device
02/24/2011US20110045649 METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH Al2O3/NANO-CRYSTALLINE Si LAYER
02/24/2011US20110045648 Methods for fabricating bulk finfet devices having deep trench isolation
02/24/2011US20110045647 Methods of forming non-volatile memory devices
02/24/2011US20110045646 Selective deposition of sige layers from single source of si-ge hydrides
02/24/2011US20110045645 High-efficiency filler cell with switchable, integrated buffer capacitance for high frequency applications
02/24/2011US20110045644 Fuse link structures using film stress for programming and methods of manufacture
02/24/2011US20110045643 Method of forming active region structure
02/24/2011US20110045642 Method of manufacturing semiconductor package
02/24/2011US20110045641 Semiconductor Device Having Solder-Free Gold Bump Contacts for Stability in Repeated Temperature Cycles
02/24/2011US20110045640 Method and system for bonding electrical devices using an electrically conductive adhesive
02/24/2011US20110045639 Photosensitive adhesive
02/24/2011US20110045638 Heat resistant masking tape and usage thereof
02/24/2011US20110045637 Ultra Thin Bumped Wafer With Under-Film
02/24/2011US20110045636 Lightweight and compact through-silicon via stack package with excellent electrical connections and method for manufacturing the same
02/24/2011US20110045635 Vertically stacked pre-packaged integrated circuit chips
02/24/2011US20110045634 Semiconductor Device and Method of Forming Dual-Active Sided Semiconductor Die in Fan-Out Wafer Level Chip Scale Package
02/24/2011US20110045633 Thin film transistor having n-type and p-type cis thin films and method of manufacturing the same
02/24/2011US20110045632 Methods of Manufacturing Solid State Image Pickup Devices
02/24/2011US20110045624 Phosphorus paste for diffusion and process for producing solar battery utilizing the phosphorus paste
02/24/2011US20110045621 Vertical cavity surface emitting laser having multiple top-side contacts
02/24/2011US20110045620 Light emitting diode integrated with lens, line printer head, and method of manufacturing the light emitting diode
02/24/2011US20110045616 Method of fabricating an ultra-small condenser microphone
02/24/2011US20110045615 Manufacturing method of semiconductor device
02/24/2011US20110045614 Method and Apparatus for Providing LED Package with Controlled Color Temperature
02/24/2011US20110045613 Method of manufacturing semiconductor device and exposure device
02/24/2011US20110045612 Methods for distinguishing a set of highly doped regions from a set of lightly doped regions on a silicon substrate
02/24/2011US20110045611 method of initiating molecular bonding
02/24/2011US20110045610 Uv treatment for carbon-containing low-k dielectric repair in semiconductor processing
02/24/2011US20110045609 Method for detaching layers with low magnetic permeability
02/24/2011US20110045411 Film adhesion device and film adhesion method
02/24/2011US20110045260 Transparent conductive laminate for a semiconductor device and method of improving color homogeneity of the same
02/24/2011US20110045246 Silicon single crystal wafer and method for manufacturing silicon single crystal wafer, and method for evaluating silicon single crystal wafer
02/24/2011US20110045244 Engineering flat surfaces on materials doped via pulsed laser irradiation
02/24/2011US20110044529 Inspection system and inspection method
02/24/2011US20110044369 Silicon carrier optoelectronic packaging