Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
10/2011
10/13/2011WO2011124061A1 Semiconductor device and method for fabricating the same
10/13/2011WO2011124059A1 High speed transistor structure and method for fabricating the same
10/13/2011WO2011124003A1 Manufacturing method for structure of metal gate/ high k gate dielectric stack layer
10/13/2011WO2011124002A1 Semiconductor structure and manufacturing method thereof
10/13/2011WO2011124001A1 Semiconductor device and manufacturing method thereof
10/13/2011WO2011124000A1 Semiconductor device and method for manufacturing the same
10/13/2011WO2011123936A1 Semiconductor memory device having a three-dimensional structure
10/13/2011WO2011094132A3 Method of reducing pattern collapse in high aspect ratio nanostructures
10/13/2011WO2011093956A3 Protruding tsv tips for enhanced heat dissipation for ic devices
10/13/2011WO2011093953A3 High voltage scrmos in bicmos process technologies
10/13/2011WO2011090583A3 Germanium-based quantum well devices
10/13/2011WO2011088156A3 Phase-modulated rf power for plasma chamber electrode
10/13/2011WO2011084532A3 Dielectric film formation using inert gas excitation
10/13/2011WO2011084269A3 Stress compensation for large area gallium nitride or other nitride-based structures on semiconductor substrates
10/13/2011WO2011084127A3 Methodology for cleaning of surface metal contamination from an upper electrode used in a plasma chamber
10/13/2011WO2011079918A3 Conductor structural element and method for producing a conductor structural element
10/13/2011WO2011077344A3 Method for monitoring the amount of contamination imparted into semiconductor wafers during wafer processing
10/13/2011WO2011072307A3 Compositions comprising base-reactive component and processes for photolithography
10/13/2011WO2011059947A3 Photoresist simulation
10/13/2011WO2011059205A3 Lead frame and manufacturing method of the same
10/13/2011WO2011054611A3 Method for the self-assembly of electrical, electronic or micromechanical components on a substrate
10/13/2011WO2011054510A3 Wafer processing
10/13/2011WO2011051791A3 Method and system for lithography hotspot correction of a post-route layout
10/13/2011WO2011032983A3 Process for the manufacture of wafers for solar cells at ambient pressure
10/13/2011WO2011032538A9 Diode array and method for producing a diode array
10/13/2011WO2011015330A3 Flange for a cvd reactor housing, use of a camera in a cvd method, and cvd method for producing silicon rods
10/13/2011US20110251713 Defect analyzer
10/13/2011US20110251075 System and method for the analysis of bodily fluids
10/13/2011US20110250824 Polishing method and polishing apparatus
10/13/2011US20110250765 Coating treatment method, non-transitory computer storage medium and coating treatment apparatus
10/13/2011US20110250764 Method of thermally treating silicon with oxygen
10/13/2011US20110250763 Plasma oxidation method and plasma oxidation apparatus
10/13/2011US20110250762 Method of cleaning and micro-etching semiconductor wafers
10/13/2011US20110250761 Plasma etching method, plasma etching apparatus, and computer-readable storage medium
10/13/2011US20110250760 Method for manufacturing a micro-electromechanical structure
10/13/2011US20110250759 Method to Reduce Charge Buildup During High Aspect Ratio Contact Etch
10/13/2011US20110250758 Plasma processing method of semiconductor manufacturing apparatus
10/13/2011US20110250757 Method of manufacturing semiconductor device
10/13/2011US20110250756 Aqueous dispersion for chemical mechanical polishing, chemical mechanical polishing method, kit for chemical mechanical polishing, and kit for preparing aqueous dispersion for chemical mechanical polishing
10/13/2011US20110250755 Method of polishing wafer surface on which copper and silicon are exposed
10/13/2011US20110250754 Polishing Composition and Polishing Method
10/13/2011US20110250753 Atomic Layer Deposition Methods
10/13/2011US20110250752 Method of manufacturing a semiconductor integrated circuit device
10/13/2011US20110250751 Method for filling metal
10/13/2011US20110250750 Method for fabricating semiconductor device
10/13/2011US20110250749 Interconnects with improved electromigration reliability
10/13/2011US20110250748 Method of manufacturing semiconductor device
10/13/2011US20110250747 Memory device and method for manufacturing memory devices
10/13/2011US20110250746 Nonvolatile memory device with multiple blocking layers and method of fabricating the same
10/13/2011US20110250745 Methods of forming patterns, and methods of forming integrated circuits
10/13/2011US20110250744 Semiconductor memory device and manufacturing method thereof
10/13/2011US20110250743 Method for producing a transistor gate with sub-photolithographic dimensions
10/13/2011US20110250742 Controlling warping in integrated circuit devices
10/13/2011US20110250741 Method of producing semiconductor device, solid-state imaging device, method of producing electric apparatus, and electric apparatus
10/13/2011US20110250740 Method and device for the treatment of a semiconductor substrate
10/13/2011US20110250739 Epitaxial wafer having a heavily doped substrate and process for the preparation thereof
10/13/2011US20110250738 Methods of selectively forming silicon-on-insulator structures using selective expitaxial growth process
10/13/2011US20110250737 Transistor with a-face conductive channel and trench protecting well region
10/13/2011US20110250736 Schottky barrier diode and method for making the same
10/13/2011US20110250735 Method for cutting an electric fuse
10/13/2011US20110250734 Specimen processing apparatus and method thereof
10/13/2011US20110250733 Thinning method and silicon wafer based structure
10/13/2011US20110250732 Orientation of an electronic cmos structure with respect to a buried structure in the case of a bonded and thinned-back stack of semiconductor wafers
10/13/2011US20110250731 Preferential dielectric gapfill
10/13/2011US20110250730 Method of Forming High Capacitance Semiconductor Capacitors with a Single Lithography Step
10/13/2011US20110250729 Method for fabricating memory
10/13/2011US20110250728 Method for manufacturing semiconductor device
10/13/2011US20110250727 Method of manufacturing flash memory device
10/13/2011US20110250726 Semiconductor device having a hetero-junction bipolar transistor and manufacturing method thereof
10/13/2011US20110250725 Method of fabricating gate electrode using a treated hard mask
10/13/2011US20110250724 Manufacturing method of semiconductor device
10/13/2011US20110250723 Manufacturing method of semiconductor device
10/13/2011US20110250722 Inverse chip connector
10/13/2011US20110250721 Stacked and shielded packages with interconnects
10/13/2011US20110250720 Thru silicon enabled die stacking scheme
10/13/2011US20110250717 Solid-state imaging device and method for manufacturing the same
10/13/2011US20110250715 Methods for forming anti-reflection structures for cmos image sensors
10/13/2011US20110250710 Electrical alignment mark set and method for aligning wafer stack
10/13/2011US20110250709 Method and apparatus for manufacturing thin film photoelectric conversion module
10/13/2011US20110250708 Method of manufacturing organic light emitting diode arrays and system for eliminating defects in organic light emitting diode arrays
10/13/2011US20110250707 Method of manufacturing semiconductor device
10/13/2011US20110250706 Method of fabricating mems, nems, photonic, micro- and nano-fabricated devices and systems
10/13/2011US20110250416 Methods of making substrate structures having a weakened intermediate layer
10/13/2011US20110250044 Device for treating disc-like article and method for operating same
10/13/2011US20110250039 Modular carrier
10/13/2011US20110249938 Optical grating coupler
10/13/2011US20110249885 Mask inspection apparatus and image generation method
10/13/2011US20110249500 Nonvolatile memory device and method for fabricating the same
10/13/2011US20110249489 Nanowire Circuits in Matched Devices
10/13/2011US20110249488 Data Cells with Drivers and Methods of Making and Operating the Same
10/13/2011US20110249160 Indium tin oxide gate charge coupled device
10/13/2011US20110249111 Process control and manufacturing method for fan out wafers
10/13/2011US20110248778 Devices comprising colossal magnetocapacitive materials and related methods
10/13/2011US20110248744 Scalable non-blocking switching network for programmable logic
10/13/2011US20110248738 Testing apparatus for electronic devices
10/13/2011US20110248412 Chip identification for organic laminate packaging and methods of manufacture
10/13/2011US20110248410 Stack packages using reconstituted wafers
10/13/2011US20110248408 Package substrate and fabricating method thereof
10/13/2011US20110248407 Process For Making a Semiconductor System
10/13/2011US20110248406 Method of Manufacturing Semiconductor Device