Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 8 - Arrangements for selecting an address in a digital store
Patents for G11C 8 - Arrangements for selecting an address in a digital store (19,368)
01/2015
01/06/2015US8929117 Multi-chip package and memory system
12/2014
12/30/2014US8924671 Semiconductor storage device and control method thereof
12/30/2014US8924639 Independently controllable and reconfigurable virtual memory devices in memory modules that are pin-compatible with standard memory modules
12/30/2014US8924286 Distribution of electronic market data
12/30/2014US8923090 Address decoding circuits for reducing address and memory enable setup time
12/30/2014US8923089 Single-port read multiple-port write storage device using single-port memory cells
12/30/2014US8923085 Low-pin-count non-volatile memory embedded in a integrated circuit without any additional pins for access
12/30/2014US8923065 Nonvolatile memory and method with improved I/O interface
12/30/2014US8923035 Junctionless semiconductor device having buried gate, apparatus including the same, and method for manufacturing the semiconductor device
12/30/2014US8922029 Apparatus having a wiring board and memory devices
12/25/2014US20140376326 Semiconductor integrated circuit
12/25/2014US20140376324 Testing through-silicon-vias
12/23/2014US8918594 Multi-interface memory with access control
12/23/2014US8917572 Semiconductor memory device and method of testing the same
12/23/2014US8917571 Configurable-width memory channels for stacked memory structures
12/23/2014US8917570 Memory device and method for operating the same
12/23/2014US8917564 Three-dimensional semiconductor memory device having compensating data skewing according to interlayer timing delay and method of de-skewing data therein
12/18/2014US20140369153 Data strobe control device
12/18/2014US20140369152 N-well switching circuit
12/18/2014US20140369151 High voltage switching circuitry for a cross-point array
12/18/2014US20140369150 Column decoders
12/18/2014US20140369149 Word line drivers and semiconductor memory devices including the same
12/18/2014US20140369148 Memory module and memory system
12/17/2014CN104217751A 一种存储器 A memory
12/16/2014US8913459 Semiconductor device including plural chips stacked to each other
12/16/2014US8913458 Integrity check of measured signal trace data
12/16/2014US8913457 Dual clock edge triggered memory
12/16/2014US8913456 SRAM with improved write operation
12/16/2014US8913455 Dual port memory cell
12/16/2014US8913436 Non-volatile memory (NVM) with word line driver/decoder using a charge pump voltage
12/11/2014US20140362657 Flexible identification technique
12/11/2014US20140362656 Memory with low current consumption and method for reducing current consumption of a memory
12/11/2014US20140362639 Integrated Circuit With Separate Supply Voltage For Memory That Is Different From Logic Circuit Supply Voltage
12/09/2014US8908467 Semiconductor memory apparatus and semiconductor system including the same
12/09/2014US8908466 Multi-column addressing mode memory system including an integrated circuit memory device
12/09/2014US8908465 Using storage cells to perform computation
12/09/2014US8908454 Memory architecture with redundant resources
12/09/2014US8908445 Non-volatile memory (NVM) with block-size-aware program/erase
12/09/2014US8908439 Adaptive word-line boost driver
12/09/2014US8908410 Nonvolatile semiconductor memory device
12/09/2014US8907698 On-die termination circuit and termination method
12/02/2014US8904096 Storage device and information processing system
12/02/2014US8902694 Integrity check of measured signal trace data
12/02/2014US8902692 Dynamic random access memory device with improved control circuitry for the word lines
12/02/2014US8902690 Decoding scheme for bipolar-based diode three-dimensional memory requiring unipolar programming
12/02/2014US8902685 Memory device and method for operating the same
12/02/2014US8902683 Memory access alignment in a double data rate (‘DDR’) system
12/02/2014US8902680 Identifying stacked dice
12/02/2014US8902679 Memory array with on and off-state wordline voltages having different temperature coefficients
12/02/2014US8902676 Wordline coupling reduction technique
12/02/2014US8902672 Methods and apparatus for designing and constructing multi-port memory circuits
12/02/2014US8902643 Apparatus, system, and method for writing multiple magnetic random access memory cells with a single field line
12/02/2014US8902628 Resistive memory device and sensing margin trimming method thereof
12/02/2014US8901567 Semiconductor device and manufacturing method thereof
11/2014
11/27/2014US20140347950 Memory Systems and Methods for Dividing Physical Memory Locations Into Temporal Memory Locations
11/27/2014US20140347949 Block selection circuit and semiconductor device having the same
11/27/2014US20140347948 Apparatuses and methods for unit identification in a master/slave memory stack
11/25/2014US8897093 Controlling method of connector, connector, and memory storage device
11/25/2014US8897081 Semiconductor memory device
11/25/2014US8897059 Resistance change memory device that stores a reversible resistance value as data
11/25/2014US8897052 Memory architecture
11/25/2014US8897050 Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
11/20/2014US20140340978 Access methods and circuits for memory devices having multiple banks
11/20/2014US20140340954 Low-Pin-Count Non-Volatile Memory Interface with Soft Programming Capability
11/18/2014US8891330 Method and apparatus for simultaneously accessing a plurality of memory cells in a memory array to perform a read operation and/or a write operation
11/18/2014US8891325 Circuit for driving word line
11/18/2014US8891317 Volatile memory with a decreased consumption
11/18/2014US8891289 Ten-transistor dual-port SRAM with shared bit-line architecture
11/18/2014US8891286 Integrated circuit, method for driving the same, and semiconductor device
11/18/2014US8890300 Discrete three-dimensional memory comprising off-die read/write-voltage generator
11/13/2014US20140334243 Write level training using dual frequencies in a double data-rate memory device interface
11/13/2014US20140334242 Semiconductor memory apparatus and method of operating using the same
11/13/2014US20140334241 Circuits, apparatuses, and methods for oscillators
11/13/2014US20140334238 Low Power Memory Device
11/13/2014US20140334235 Memory macro configuration and method
11/11/2014US8886892 Memory module and method employing a multiplexer to replace a memory device
11/11/2014US8885439 Systems and methods including clock features such as minimization of simultaneous switching outputs (SSO) effects involving echo clocks
11/11/2014US8885438 Startup circuit detecting stable system clock
11/11/2014US8885437 Storage device and driving method thereof
11/11/2014US8885436 Semiconductor memory device and method of driving the same
11/11/2014US8885399 Phase change memory (PCM) architecture and a method for writing into PCM architecture
11/11/2014US8885389 Continuous mesh three dimensional non-volatile storage with vertical select devices
11/11/2014US8885381 Three dimensional non-volatile storage with dual gated vertical select devices
11/11/2014US8884666 Clock generator
11/04/2014US8879351 Non-volatile memory bank and page buffer therefor
11/04/2014US8879342 Memory devices, systems and methods employing command/address calibration
11/04/2014US8879334 Semiconductor device having timing control for read-write memory access operations
11/04/2014US8879316 Semiconductor device and method of generating voltages using the same
11/04/2014US8879311 Phase change memory word line driver
11/04/2014US8879308 Raising programming currents of magnetic tunnel junctions using word line overdrive and high-k metal gate
11/04/2014US8879304 Memory circuit and word line control circuit
11/04/2014US8879303 Pre-charge tracking of global read lines in high speed SRAM
11/04/2014US8878860 Accessing memory using multi-tiling
10/2014
10/30/2014US20140321190 Vertical switch three-dimensional memory array
10/28/2014US8873331 Command decoders
10/28/2014US8873330 Semiconductor memory device
10/28/2014US8873329 Patterned memory page activation
10/28/2014US8873313 Semiconductor apparatus
10/28/2014US8873312 Decoder circuit of semiconductor storage device
10/28/2014US8873304 Integrated circuitry, chip, method for testing a memory device, method for manufacturing an integrated circuit and method for manufacturing a chip
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