| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 10/19/1999 | US5970021 Synchronous semiconductor memory device having function of inhibiting output of invalid data |
| 10/19/1999 | US5970016 Dynamic semiconductor memory device with banks capable of operating independently |
| 10/19/1999 | US5970015 Semiconductor integrated circuit device allowing change of product specification and chip screening method therewith |
| 10/19/1999 | US5970014 Semiconductor memory device having two or more memory blocks |
| 10/19/1999 | US5970010 Semiconductor memory device |
| 10/19/1999 | US5970007 Semiconductor integrated circuit device |
| 10/19/1999 | US5970006 Semiconductor memory device having cell array divided into a plurality of cell blocks |
| 10/19/1999 | US5969999 Merged memory logic integrated circuits including buffers driven by adjustably delayed clock signals |
| 10/19/1999 | US5969998 MOS semiconductor device with memory cells each having storage capacitor and transfer transistor |
| 10/19/1999 | US5969996 Semiconductor memory device and memory system |
| 10/19/1999 | US5969990 Nonvolatile memory array with NAND string memory cell groups selectively connected to sub bit lines |
| 10/19/1999 | US5969986 High-bandwidth read and write architectures for non-volatile memories |
| 10/19/1999 | US5969985 Nonvolatile semiconductor memory device |
| 10/19/1999 | US5969984 Level converting circuit for converting level of an input signal, internal potential generating circuit for generating internal potential, internal potential generating unit generating internal potential, highly reliable semiconductor device |
| 10/19/1999 | US5969977 Electronic memory device having bit lines with block selector switches |
| 10/19/1999 | US5969654 Multi-channel recording system for a general purpose computer |
| 10/14/1999 | DE19916348A1 Synchronous semiconductor memory device with response to an external masking signal to force the entry of a data connection in the high impedance state |
| 10/14/1999 | DE19830568A1 Ferroelectric memory storage arrangement |
| 10/13/1999 | EP0949630A2 Clock suspending circuitry |
| 10/13/1999 | EP0948792A1 Method and apparatus for sharing sense amplifiers between memory banks |
| 10/13/1999 | CN1231480A Bus central point holding circuit for high-speed memory read operation |
| 10/13/1999 | CN1231479A SDRAM structure for sequence pulse string mode |
| 10/12/1999 | US5966731 Protocol for communication with dynamic memory |
| 10/12/1999 | US5966725 Memory refreshing system having selective execution of self and normal refresh operations for a plurality of memory banks |
| 10/12/1999 | US5966724 Synchronous memory device with dual page and burst mode operations |
| 10/12/1999 | US5966343 Variable latency memory circuit |
| 10/12/1999 | US5966342 Write control driver circuit and method |
| 10/12/1999 | US5966341 Semiconductor memory |
| 10/12/1999 | US5966340 Semiconductor memory device having hierarchical word line structure |
| 10/12/1999 | US5966338 Integrated circuit |
| 10/12/1999 | US5966337 Method for overdriving bit line sense amplifier |
| 10/12/1999 | US5966336 Semiconductor device having redundancy circuit |
| 10/12/1999 | US5966334 Device and method for repairing a memory array by storing each bit in multiple memory cells in the array |
| 10/12/1999 | US5966320 SRAM structure having common bit line |
| 10/12/1999 | US5966317 Memory cell |
| 10/12/1999 | US5966315 Semiconductor memory having hierarchical bit line architecture with non-uniform local bit lines |
| 10/12/1999 | US5966045 Semiconductor device having a first stage input unit to which a potential is supplied from external and internal power supplies |
| 10/12/1999 | US5966021 Apparatus for testing an integrated circuit in an oven during burn-in |
| 10/12/1999 | US5965925 Integrated circuit layout methods and layout structures |
| 10/12/1999 | US5964884 Self-timed pulse control circuit |
| 10/12/1999 | CA2155791C Video memory arrangement |
| 10/07/1999 | WO1999050852A1 Semiconductor memory asynchronous pipeline |
| 10/07/1999 | DE19915044A1 Interface for synchronous semiconductor memory e.g. SDRAM |
| 10/06/1999 | EP0947992A2 Sense amplifier circuit |
| 10/06/1999 | EP0947991A2 Improved dynamic random assess memory circuit and methods therefor |
| 10/06/1999 | EP0946943A1 Memory and method for sensing sub-groups of memory elements |
| 10/06/1999 | EP0946542A1 Indane or dihydroindole derivatives |
| 10/06/1999 | CN1230750A Static semiconductor memory device operating at high speed under lower power supply voltage |
| 10/06/1999 | CN1045502C Read amplifier circuit and semiconductor memory element |
| 10/05/1999 | US5963960 Method and apparatus for queuing updates in a computer system |
| 10/05/1999 | US5963504 Address transition detection in a synchronous design |
| 10/05/1999 | US5963503 Synchronous systems having secondary caches |
| 10/05/1999 | US5963502 Clock-synchronous type semiconductor memory device capable of outputting read clock signal at correct timing |
| 10/05/1999 | US5963501 Dynamic clock signal generating circuit for use in synchronous dynamic random access memory devices |
| 10/05/1999 | US5963496 Sense amplifier with zero power idle mode |
| 10/05/1999 | US5963495 Dynamic sense amplifier with embedded latch |
| 10/05/1999 | US5963494 Semiconductor memory having bitline precharge circuit |
| 10/05/1999 | US5963493 Memory device communication line control |
| 10/05/1999 | US5963488 Semiconductor memory device |
| 10/05/1999 | US5963487 Write enabling circuitry for a semiconductor memory |
| 10/05/1999 | US5963486 Bit switch circuit and bit line selection method |
| 10/05/1999 | US5963485 Method and apparatus for bit line recovery in dynamic random access memory |
| 10/05/1999 | US5963484 High speed single-ended amplifier of a latched type |
| 10/05/1999 | US5963483 Synchronous memory unit |
| 10/05/1999 | US5963482 Memory integrated circuit with shared read/write line |
| 10/05/1999 | US5963481 Integrated circuit |
| 10/05/1999 | US5963468 Low latency memories and systems using the same |
| 10/05/1999 | US5963465 Symmetric segmented memory array architecture |
| 10/05/1999 | US5963077 For a semiconductor memory device |
| 10/05/1999 | US5963060 Latching sense amplifier |
| 10/05/1999 | US5962899 Electrostatic discharge protection circuit |
| 10/01/1999 | CA2805213A1 Semiconductor memory asynchronous pipeline |
| 10/01/1999 | CA2267870A1 A linear surface memory to spatial tiling algorithm/mechanism |
| 09/30/1999 | WO1999031711A3 Precharge circuit for semiconductor memory device |
| 09/29/1999 | CN1230027A Semiconductor memory device |
| 09/29/1999 | CN1229994A 半导体存储器件 A semiconductor memory device |
| 09/29/1999 | CN1229992A Memory address generator circuit and semiconductor memory device |
| 09/29/1999 | CN1229991A Memory device with data output buffer and control method thereof |
| 09/28/1999 | US5959937 Dual clocking scheme in a multi-port RAM |
| 09/28/1999 | US5959936 Column select line enable circuit for a semiconductor memory device |
| 09/28/1999 | US5959935 Synchronization signal generation circuit and method |
| 09/28/1999 | US5959933 System for improved memory cell access |
| 09/28/1999 | US5959931 Memory system having multiple reading and writing ports |
| 09/28/1999 | US5959930 Multi-bank synchronous semiconductor memory device |
| 09/28/1999 | US5959929 Method for writing to multiple banks of a memory device |
| 09/28/1999 | US5959927 Semiconductor integrated circuit device having hierarchical power source arrangement |
| 09/28/1999 | US5959926 Programmable power supply systems and methods providing a write protected memory having multiple interface capability |
| 09/28/1999 | US5959924 Method and circuit for controlling an isolation gate in a semiconductor memory device |
| 09/28/1999 | US5959921 Sense amplifier for complement or no-complementary data signals |
| 09/28/1999 | US5959920 Semiconductor memory device using sense amplifiers in a dummy cell area for increasing writing speed |
| 09/28/1999 | US5959919 Low power sense amplifier for semiconductor memory devices |
| 09/28/1999 | US5959918 Semiconductor memory device having improved manner of data line connection in hierarchical data line structure |
| 09/28/1999 | US5959916 Write driver and bit line precharge apparatus and method |
| 09/28/1999 | US5959908 Semiconductor memory device having spare word lines |
| 09/28/1999 | US5959907 Semiconductor memory device having a redundancy circuit |
| 09/28/1999 | US5959906 Semiconductor memory device with a fully accessible redundant memory cell array |
| 09/28/1999 | US5959904 Dynamic column redundancy driving circuit for synchronous semiconductor memory device |
| 09/28/1999 | US5959901 Static semiconductor memory of flip-flop circuit type with driving N-channel transistors |
| 09/28/1999 | US5959900 Synchronous semiconductor memory having a reduced number of registers |
| 09/28/1999 | US5959899 Semiconductor memory having single path data pipeline for CAS-latency |